drm/i915/skl: Derive the max CDCLK from DFSM

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 89fd7c8a1525729e706ff2a599db227d97918b1c..760dbebc1aefc39e3bcda25fe987330a8a7d20d7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5761,6 +5761,13 @@ enum skl_disp_power_wells {
 #define HSW_NDE_RSTWRN_OPT     0x46408
 #define  RESET_PCH_HANDSHAKE_ENABLE    (1<<4)
 
+#define SKL_DFSM                       0x51000
+#define SKL_DFSM_CDCLK_LIMIT_MASK      (3 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_675       (0 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_540       (1 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_450       (2 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_337_5     (3 << 23)
+
 #define FF_SLICE_CS_CHICKEN2                   0x20e4
 #define  GEN9_TSG_BARRIER_ACK_DISABLE          (1<<8)
 

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7e8b583527e9b73b69765da62fa79bbafe984769..9280e76505fce70baf93b219d3e7b66d8b0bb106 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5751,7 +5751,18 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
 
-       if (IS_BROADWELL(dev))  {
+       if (IS_SKYLAKE(dev)) {
+               u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
+
+               if (limit == SKL_DFSM_CDCLK_LIMIT_675)
+                       dev_priv->max_cdclk_freq = 675000;
+               else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
+                       dev_priv->max_cdclk_freq = 540000;
+               else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
+                       dev_priv->max_cdclk_freq = 450000;
+               else
+                       dev_priv->max_cdclk_freq = 337500;
+       } else if (IS_BROADWELL(dev))  {
                /*
                 * FIXME with extra cooling we can allow
                 * 540 MHz for ULX and 675 Mhz for ULT.