Regernate cgen built files.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1d5247d1f5fb4d9327ebe4bb61f4d8cbd46c6ce2..d16b5b603ab3494d8d8bf33840bfa4397e49c27c 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,18 @@
+2002-05-15  Nick Clifton  <nickc@cambridge.redhat.com>
+
+       * fr30-asm.c: Regenerate.
+       * fr30-desc.c: Regenerate.
+       * fr30-dis.c: Regenerate.
+       * m32r-asm.c: Regenerate.
+       * m32r-desc.c: Regenerate.
+       * m32r-dis.c: Regenerate.
+       * openrisc-asm.c: Regenerate.
+       * openrisc-desc.c: Regenerate.
+       * openrisc-dis.c: Regenerate.
+       * xstormy16-asm.c: Regenerate.
+       * xstormy16-desc.c: Regenerate.
+       * xstormy16-dis.c: Regenerate.
+
 2002-05-15  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
 
        * mips-dis.c (is_newabi): EABI is not a NewABI.

diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c
index 40f015ad0358519639c294e15745872d7a1f4ae0..be9c36c947c2eca4c88e79490a47fbb21ed2dc0d 100644 (file)
--- a/opcodes/fr30-asm.c
+++ b/opcodes/fr30-asm.c
@@ -571,7 +571,7 @@ parse_insn_normal (cd, insn, strp, fields)
        }
 
       /* We have an operand of some sort.  */
-      errmsg = fr30_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+      errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
                                          &str, fields);
       if (errmsg)
        return errmsg;

diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c
index fd6afee7d2d3b4fc7c67e005a86e951cc1ea9553..18963b9f1687bf0b92eb5324289574d6a7873f01 100644 (file)
--- a/opcodes/fr30-desc.c
+++ b/opcodes/fr30-desc.c
@@ -1747,10 +1747,43 @@ void
 fr30_cgen_cpu_close (cd)
      CGEN_CPU_DESC cd;
 {
+  unsigned int i;
+  CGEN_INSN *insns;
+
+  if (cd->macro_insn_table.init_entries)
+    {
+      insns = cd->macro_insn_table.init_entries;
+      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+       {
+         if (CGEN_INSN_RX ((insns)))
+           regfree(CGEN_INSN_RX (insns));
+       }
+    }
+
+  if (cd->insn_table.init_entries)
+    {
+      insns = cd->insn_table.init_entries;
+      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+       {
+         if (CGEN_INSN_RX (insns))
+           regfree(CGEN_INSN_RX (insns));
+       }
+    }
+
+  
+
+  if (cd->macro_insn_table.init_entries)
+    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
   if (cd->insn_table.init_entries)
     free ((CGEN_INSN *) cd->insn_table.init_entries);
+
   if (cd->hw_table.entries)
     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+  if (cd->operand_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
   free (cd);
 }
 

diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c
index 961ce220290cfc6c2a0d9880e5bf1203c44854c4..7affa860f4f0d4130a4728980d7658d72b8d8446 100644 (file)
--- a/opcodes/fr30-dis.c
+++ b/opcodes/fr30-dis.c
@@ -632,11 +632,21 @@ default_print_insn (cd, pc, info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
+typedef struct cpu_desc_list {
+  struct cpu_desc_list *next;
+  int isa;
+  int mach;
+  int endian;
+  CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
 int
 print_insn_fr30 (pc, info)
      bfd_vma pc;
      disassemble_info *info;
 {
+  static cpu_desc_list *cd_list = 0;
+  cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
   static int prev_isa;
   static int prev_mach;
@@ -667,18 +677,27 @@ print_insn_fr30 (pc, info)
 #ifdef CGEN_COMPUTE_ISA
   isa = CGEN_COMPUTE_ISA (info);
 #else
-  isa = 0;
+  isa = info->insn_sets;
 #endif
 
-  /* If we've switched cpu's, close the current table and open a new one.  */
+  /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
       && (isa != prev_isa
          || mach != prev_mach
          || endian != prev_endian))
     {
-      fr30_cgen_cpu_close (cd);
       cd = 0;
-    }
+      for (cl = cd_list; cl; cl = cl->next)
+       {
+         if (cl->isa == isa &&
+             cl->mach == mach &&
+             cl->endian == endian)
+           {
+             cd = cl->cd;
+             break;
+           }
+       }
+    } 
 
   /* If we haven't initialized yet, initialize the opcode table.  */
   if (! cd)
@@ -699,6 +718,16 @@ print_insn_fr30 (pc, info)
                                 CGEN_CPU_OPEN_END);
       if (!cd)
        abort ();
+
+      /* save this away for future reference */
+      cl = xmalloc (sizeof (struct cpu_desc_list));
+      cl->cd = cd;
+      cl->isa = isa;
+      cl->mach = mach;
+      cl->endian = endian;
+      cl->next = cd_list;
+      cd_list = cl;
+
       fr30_cgen_init_dis (cd);
     }
 

diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index 718dd994ce166f6bcc890082aca24eb65092e80c..4abe187b81f2e222e514a20bdfa4414df606a622 100644 (file)
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -573,7 +573,7 @@ parse_insn_normal (cd, insn, strp, fields)
        }
 
       /* We have an operand of some sort.  */
-      errmsg = m32r_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+      errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
                                          &str, fields);
       if (errmsg)
        return errmsg;

diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 4acf72044c566e8e92ab2aa29038b1e31418383a..de7bde44fdc9293a7a56a22085a65ecaeb0e27f9 100644 (file)
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -1441,10 +1441,43 @@ void
 m32r_cgen_cpu_close (cd)
      CGEN_CPU_DESC cd;
 {
+  unsigned int i;
+  CGEN_INSN *insns;
+
+  if (cd->macro_insn_table.init_entries)
+    {
+      insns = cd->macro_insn_table.init_entries;
+      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+       {
+         if (CGEN_INSN_RX ((insns)))
+           regfree(CGEN_INSN_RX (insns));
+       }
+    }
+
+  if (cd->insn_table.init_entries)
+    {
+      insns = cd->insn_table.init_entries;
+      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+       {
+         if (CGEN_INSN_RX (insns))
+           regfree(CGEN_INSN_RX (insns));
+       }
+    }
+
+  
+
+  if (cd->macro_insn_table.init_entries)
+    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
   if (cd->insn_table.init_entries)
     free ((CGEN_INSN *) cd->insn_table.init_entries);
+
   if (cd->hw_table.entries)
     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+  if (cd->operand_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
   free (cd);
 }
 

diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index 40d7679907ebf01b807019ba0c2f72e04d56aa0f..07560e15ff5059d7019dc9c8abc1f6e97d35e625 100644 (file)
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -563,11 +563,21 @@ default_print_insn (cd, pc, info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
+typedef struct cpu_desc_list {
+  struct cpu_desc_list *next;
+  int isa;
+  int mach;
+  int endian;
+  CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
 int
 print_insn_m32r (pc, info)
      bfd_vma pc;
      disassemble_info *info;
 {
+  static cpu_desc_list *cd_list = 0;
+  cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
   static int prev_isa;
   static int prev_mach;
@@ -598,18 +608,27 @@ print_insn_m32r (pc, info)
 #ifdef CGEN_COMPUTE_ISA
   isa = CGEN_COMPUTE_ISA (info);
 #else
-  isa = 0;
+  isa = info->insn_sets;
 #endif
 
-  /* If we've switched cpu's, close the current table and open a new one.  */
+  /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
       && (isa != prev_isa
          || mach != prev_mach
          || endian != prev_endian))
     {
-      m32r_cgen_cpu_close (cd);
       cd = 0;
-    }
+      for (cl = cd_list; cl; cl = cl->next)
+       {
+         if (cl->isa == isa &&
+             cl->mach == mach &&
+             cl->endian == endian)
+           {
+             cd = cl->cd;
+             break;
+           }
+       }
+    } 
 
   /* If we haven't initialized yet, initialize the opcode table.  */
   if (! cd)
@@ -630,6 +649,16 @@ print_insn_m32r (pc, info)
                                 CGEN_CPU_OPEN_END);
       if (!cd)
        abort ();
+
+      /* save this away for future reference */
+      cl = xmalloc (sizeof (struct cpu_desc_list));
+      cl->cd = cd;
+      cl->isa = isa;
+      cl->mach = mach;
+      cl->endian = endian;
+      cl->next = cd_list;
+      cd_list = cl;
+
       m32r_cgen_init_dis (cd);
     }
 

diff --git a/opcodes/openrisc-asm.c b/opcodes/openrisc-asm.c
index 96a6c4d2b7b3d2ea8815dec0c2680d05461b0aeb..d47659b8c8fdf041a5b58666b09721db34c8555f 100644 (file)
--- a/opcodes/openrisc-asm.c
+++ b/opcodes/openrisc-asm.c
@@ -492,7 +492,7 @@ parse_insn_normal (cd, insn, strp, fields)
        }
 
       /* We have an operand of some sort.  */
-      errmsg = openrisc_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+      errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
                                          &str, fields);
       if (errmsg)
        return errmsg;

diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c
index e5eded9e73cfa3ff9cc1a396c91485f73167d647..f66514c002ba4dec6ba8371c2a70b3e236bc9a32 100644 (file)
--- a/opcodes/openrisc-desc.c
+++ b/opcodes/openrisc-desc.c
@@ -1017,10 +1017,43 @@ void
 openrisc_cgen_cpu_close (cd)
      CGEN_CPU_DESC cd;
 {
+  unsigned int i;
+  CGEN_INSN *insns;
+
+  if (cd->macro_insn_table.init_entries)
+    {
+      insns = cd->macro_insn_table.init_entries;
+      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+       {
+         if (CGEN_INSN_RX ((insns)))
+           regfree(CGEN_INSN_RX (insns));
+       }
+    }
+
+  if (cd->insn_table.init_entries)
+    {
+      insns = cd->insn_table.init_entries;
+      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+       {
+         if (CGEN_INSN_RX (insns))
+           regfree(CGEN_INSN_RX (insns));
+       }
+    }
+
+  
+
+  if (cd->macro_insn_table.init_entries)
+    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
   if (cd->insn_table.init_entries)
     free ((CGEN_INSN *) cd->insn_table.init_entries);
+
   if (cd->hw_table.entries)
     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+  if (cd->operand_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
   free (cd);
 }
 

diff --git a/opcodes/openrisc-dis.c b/opcodes/openrisc-dis.c
index 628a86c8304949bdfedd9be661a54406880ac97e..e6a7d6a9d8520c8850ded90729751ff9866128e8 100644 (file)
--- a/opcodes/openrisc-dis.c
+++ b/opcodes/openrisc-dis.c
@@ -450,11 +450,21 @@ default_print_insn (cd, pc, info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
+typedef struct cpu_desc_list {
+  struct cpu_desc_list *next;
+  int isa;
+  int mach;
+  int endian;
+  CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
 int
 print_insn_openrisc (pc, info)
      bfd_vma pc;
      disassemble_info *info;
 {
+  static cpu_desc_list *cd_list = 0;
+  cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
   static int prev_isa;
   static int prev_mach;
@@ -485,18 +495,27 @@ print_insn_openrisc (pc, info)
 #ifdef CGEN_COMPUTE_ISA
   isa = CGEN_COMPUTE_ISA (info);
 #else
-  isa = 0;
+  isa = info->insn_sets;
 #endif
 
-  /* If we've switched cpu's, close the current table and open a new one.  */
+  /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
       && (isa != prev_isa
          || mach != prev_mach
          || endian != prev_endian))
     {
-      openrisc_cgen_cpu_close (cd);
       cd = 0;
-    }
+      for (cl = cd_list; cl; cl = cl->next)
+       {
+         if (cl->isa == isa &&
+             cl->mach == mach &&
+             cl->endian == endian)
+           {
+             cd = cl->cd;
+             break;
+           }
+       }
+    } 
 
   /* If we haven't initialized yet, initialize the opcode table.  */
   if (! cd)
@@ -517,6 +536,16 @@ print_insn_openrisc (pc, info)
                                 CGEN_CPU_OPEN_END);
       if (!cd)
        abort ();
+
+      /* save this away for future reference */
+      cl = xmalloc (sizeof (struct cpu_desc_list));
+      cl->cd = cd;
+      cl->isa = isa;
+      cl->mach = mach;
+      cl->endian = endian;
+      cl->next = cd_list;
+      cd_list = cl;
+
       openrisc_cgen_init_dis (cd);
     }
 

diff --git a/opcodes/xstormy16-asm.c b/opcodes/xstormy16-asm.c
index 3f26b18562ccb9ada3eedd540961bc82033153dc..047339dadd8423cbf47a7869d41ea1c543474402 100644 (file)
--- a/opcodes/xstormy16-asm.c
+++ b/opcodes/xstormy16-asm.c
@@ -479,7 +479,7 @@ parse_insn_normal (cd, insn, strp, fields)
        }
 
       /* We have an operand of some sort.  */
-      errmsg = xstormy16_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+      errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
                                          &str, fields);
       if (errmsg)
        return errmsg;

diff --git a/opcodes/xstormy16-desc.c b/opcodes/xstormy16-desc.c
index 41da91ba9c763f62a0ea2d3466d3af45472463c3..0c506252e4580a7d86c477080c64fe3c66843707 100644 (file)
--- a/opcodes/xstormy16-desc.c
+++ b/opcodes/xstormy16-desc.c
@@ -1458,10 +1458,43 @@ void
 xstormy16_cgen_cpu_close (cd)
      CGEN_CPU_DESC cd;
 {
+  unsigned int i;
+  CGEN_INSN *insns;
+
+  if (cd->macro_insn_table.init_entries)
+    {
+      insns = cd->macro_insn_table.init_entries;
+      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+       {
+         if (CGEN_INSN_RX ((insns)))
+           regfree(CGEN_INSN_RX (insns));
+       }
+    }
+
+  if (cd->insn_table.init_entries)
+    {
+      insns = cd->insn_table.init_entries;
+      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+       {
+         if (CGEN_INSN_RX (insns))
+           regfree(CGEN_INSN_RX (insns));
+       }
+    }
+
+  
+
+  if (cd->macro_insn_table.init_entries)
+    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
   if (cd->insn_table.init_entries)
     free ((CGEN_INSN *) cd->insn_table.init_entries);
+
   if (cd->hw_table.entries)
     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+  if (cd->operand_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
   free (cd);
 }
 

diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c
index bd6c593f4940a54a5328b120820d0ea0eb1dcc4f..f3cc8e6327ac6f674b8402aedabd9192debe6309 100644 (file)
--- a/opcodes/xstormy16-dis.c
+++ b/opcodes/xstormy16-dis.c
@@ -483,11 +483,21 @@ default_print_insn (cd, pc, info)
    Print one instruction from PC on INFO->STREAM.
    Return the size of the instruction (in bytes).  */
 
+typedef struct cpu_desc_list {
+  struct cpu_desc_list *next;
+  int isa;
+  int mach;
+  int endian;
+  CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
 int
 print_insn_xstormy16 (pc, info)
      bfd_vma pc;
      disassemble_info *info;
 {
+  static cpu_desc_list *cd_list = 0;
+  cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
   static int prev_isa;
   static int prev_mach;
@@ -518,18 +528,27 @@ print_insn_xstormy16 (pc, info)
 #ifdef CGEN_COMPUTE_ISA
   isa = CGEN_COMPUTE_ISA (info);
 #else
-  isa = 0;
+  isa = info->insn_sets;
 #endif
 
-  /* If we've switched cpu's, close the current table and open a new one.  */
+  /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
       && (isa != prev_isa
          || mach != prev_mach
          || endian != prev_endian))
     {
-      xstormy16_cgen_cpu_close (cd);
       cd = 0;
-    }
+      for (cl = cd_list; cl; cl = cl->next)
+       {
+         if (cl->isa == isa &&
+             cl->mach == mach &&
+             cl->endian == endian)
+           {
+             cd = cl->cd;
+             break;
+           }
+       }
+    } 
 
   /* If we haven't initialized yet, initialize the opcode table.  */
   if (! cd)
@@ -550,6 +569,16 @@ print_insn_xstormy16 (pc, info)
                                 CGEN_CPU_OPEN_END);
       if (!cd)
        abort ();
+
+      /* save this away for future reference */
+      cl = xmalloc (sizeof (struct cpu_desc_list));
+      cl->cd = cd;
+      cl->isa = isa;
+      cl->mach = mach;
+      cl->endian = endian;
+      cl->next = cd_list;
+      cd_list = cl;
+
       xstormy16_cgen_init_dis (cd);
     }