/* tc-m32r.c -- Assembler for the Mitsubishi M32R.
- Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation.
+ Copyright (C) 1996, 1997, 1998, 1999, 2000
+ Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
#include <stdio.h>
#include <ctype.h>
#include "as.h"
-#include "subsegs.h"
+#include "subsegs.h"
#include "symcat.h"
#include "opcodes/m32r-desc.h"
#include "opcodes/m32r-opc.h"
typedef struct sym_link
{
struct sym_link *next;
- symbolS *symbol;
+ symbolS *symbol;
} sym_linkS;
-static sym_linkS *debug_sym_link = (sym_linkS *)0;
-
+static sym_linkS *debug_sym_link = (sym_linkS *) 0;
+
/* Structure to hold all of the different components describing
an individual instruction. */
typedef struct
{
- const CGEN_INSN * insn;
- const CGEN_INSN * orig_insn;
- CGEN_FIELDS fields;
+ const CGEN_INSN *insn;
+ const CGEN_INSN *orig_insn;
+ CGEN_FIELDS fields;
#if CGEN_INT_INSN_P
- CGEN_INSN_INT buffer [1];
+ CGEN_INSN_INT buffer[1];
#define INSN_VALUE(buf) (*(buf))
#else
- unsigned char buffer [CGEN_MAX_INSN_SIZE];
+ unsigned char buffer[CGEN_MAX_INSN_SIZE];
#define INSN_VALUE(buf) (buf)
#endif
- char * addr;
- fragS * frag;
- int num_fixups;
- fixS * fixups [GAS_CGEN_MAX_FIXUPS];
- int indices [MAX_OPERAND_INSTANCES];
- sym_linkS *debug_sym_link;
+ char *addr;
+ fragS *frag;
+ int num_fixups;
+ fixS *fixups[GAS_CGEN_MAX_FIXUPS];
+ int indices[MAX_OPERAND_INSTANCES];
+ sym_linkS *debug_sym_link;
}
m32r_insn;
/* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
boundary (i.e. was the first of two 16 bit insns). */
-static m32r_insn prev_insn;
+static m32r_insn prev_insn;
/* Non-zero if we've seen a relaxable insn since the last 32 bit
alignment request. */
This flag does not apply to them. */
static int m32r_relax;
-#if 0 /* not supported yet */
+#if 0
+/* Not supported yet. */
/* If non-NULL, pointer to cpu description file to read.
This allows runtime additions to the assembler. */
-static const char * m32r_cpu_desc;
+static const char *m32r_cpu_desc;
#endif
/* Non-zero if warn when a high/shigh reloc has no matching low reloc.
/* Non-zero if insns can be made parallel. */
static int optimize;
-/* stuff for .scomm symbols. */
+/* Stuff for .scomm symbols. */
static segT sbss_section;
static asection scom_section;
static asymbol scom_symbol;
struct m32r_hi_fixup
{
- struct m32r_hi_fixup * next; /* Next HI fixup. */
- fixS * fixp; /* This fixup. */
- segT seg; /* The section this fixup is in. */
+ /* Next HI fixup. */
+ struct m32r_hi_fixup *next;
+
+ /* This fixup. */
+ fixS *fixp;
+ /* The section this fixup is in. */
+ segT seg;
};
/* The list of unmatched HI relocs. */
-static struct m32r_hi_fixup * m32r_hi_fixup_list;
-
+static struct m32r_hi_fixup *m32r_hi_fixup_list;
\f
static void
allow_m32rx (on)
}
\f
#define M32R_SHORTOPTS "O"
-const char * md_shortopts = M32R_SHORTOPTS;
+
+const char *md_shortopts = M32R_SHORTOPTS;
struct option md_longopts[] =
{
{"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
{"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
-#if 0 /* not supported yet */
+#if 0
+ /* Not supported yet. */
#define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1)
#define OPTION_CPU_DESC (OPTION_RELAX + 1)
{"relax", no_argument, NULL, OPTION_RELAX},
#endif
{NULL, no_argument, NULL, 0}
};
+
size_t md_longopts_size = sizeof (md_longopts);
int
md_parse_option (c, arg)
- int c;
- char * arg;
+ int c;
+ char *arg;
{
switch (c)
{
case OPTION_M32R:
allow_m32rx (0);
break;
-
+
case OPTION_M32RX:
allow_m32rx (1);
break;
-
+
case OPTION_WARN_PARALLEL:
warn_explicit_parallel_conflicts = 1;
break;
-
+
case OPTION_NO_WARN_PARALLEL:
warn_explicit_parallel_conflicts = 0;
break;
case OPTION_NO_WARN_UNMATCHED:
warn_unmatched_high = 0;
break;
-
-#if 0 /* not supported yet */
+
+#if 0
+ /* Not supported yet. */
case OPTION_RELAX:
m32r_relax = 1;
break;
default:
return 0;
}
-
+
return 1;
}
void
md_show_usage (stream)
- FILE * stream;
+ FILE *stream;
{
fprintf (stream, _(" M32R specific command line options:\n"));
fprintf (stream, _("\
-cpu-desc provide runtime cpu description file\n"));
#endif
-}
+}
static void fill_insn PARAMS ((int));
static void m32r_scomm PARAMS ((int));
{ "fillinsn", fill_insn, 0 },
{ "scomm", m32r_scomm, 0 },
{ "debugsym", debug_sym, 0 },
- /* Not documented as so far there is no need for them.... */
+ /* Not documented as so far there is no need for them.... */
{ "m32r", allow_m32rx, 0 },
{ "m32rx", allow_m32rx, 1 },
{ NULL, NULL, 0 }
/* FIXME: Should be machine generated. */
#define NOP_INSN 0x7000
-#define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
+#define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
/* When we align the .text section, insert the correct NOP pattern.
N is the power of 2 alignment. LEN is the length of pattern FILL.
int
m32r_do_align (n, fill, len, max)
- int n;
- const char * fill;
- int len;
- int max;
+ int n;
+ const char *fill;
+ int len;
+ int max;
{
/* Only do this if the fill pattern wasn't specified. */
if (fill == NULL
frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
max ? max - 2 : 0);
}
-
+
prev_insn.insn = NULL;
return 1;
}
name = input_line_pointer;
delim = get_symbol_end ();
end_name = input_line_pointer;
-
+
if ((symbolP = symbol_find (name)) == NULL
&& (symbolP = md_undefined_symbol (name)) == NULL)
{
return;
(void) m32r_do_align (align, NULL, 0, 0);
- for (; syms != (sym_linkS *)0; syms = next_syms)
+ for (; syms != (sym_linkS *) 0; syms = next_syms)
{
symbolS *symbolP = syms->symbol;
next_syms = syms->next;
input_line_pointer = ".\n";
pseudo_set (symbolP);
- free ((char *)syms);
+ free ((char *) syms);
}
input_line_pointer = save_input_line;
{
if (prev_seg != NULL)
{
- segT seg = now_seg;
+ segT seg = now_seg;
subsegT subseg = now_subseg;
subseg_set (prev_seg, prev_subseg);
-
+
fill_insn (0);
subseg_set (seg, subseg);
if (done && debug_sym_link)
{
expand_debug_syms (debug_sym_link, 1);
- debug_sym_link = (sym_linkS *)0;
+ debug_sym_link = (sym_linkS *) 0;
}
return 1;
md_begin ()
{
flagword applicable;
- segT seg;
- subsegT subseg;
+ segT seg;
+ subsegT subseg;
/* Initialize the `cgen' interface. */
-
+
/* Set the machine number and endian. */
gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
CGEN_CPU_OPEN_ENDIAN,
/* This is a callback from cgen to gas to parse operands. */
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
-#if 0 /* not supported yet */
+#if 0
+ /* Not supported yet. */
/* If a runtime cpu description file was provided, parse it. */
if (m32r_cpu_desc != NULL)
{
- const char * errmsg;
+ const char *errmsg;
errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc);
if (errmsg != NULL)
/* The sbss section is for local .scomm symbols. */
sbss_section = subseg_new (".sbss", 0);
-
+
/* This is copied from perform_an_assembly_pass. */
applicable = bfd_applicable_section_flags (stdoutput);
bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
-
-#if 0 /* What does this do? [see perform_an_assembly_pass] */
+
+#if 0
+ /* What does this do? [see perform_an_assembly_pass] */
seg_info (bss_section)->bss = 1;
#endif
but with the name .scommon. */
scom_section = bfd_com_section;
scom_section.name = ".scommon";
- scom_section.output_section = & scom_section;
- scom_section.symbol = & scom_symbol;
- scom_section.symbol_ptr_ptr = & scom_section.symbol;
- scom_symbol = * bfd_com_section.symbol;
+ scom_section.output_section = &scom_section;
+ scom_section.symbol = &scom_symbol;
+ scom_section.symbol_ptr_ptr = &scom_section.symbol;
+ scom_symbol = *bfd_com_section.symbol;
scom_symbol.name = ".scommon";
- scom_symbol.section = & scom_section;
+ scom_symbol.section = &scom_section;
allow_m32rx (enable_m32rx);
}
static int
first_writes_to_seconds_operands (a, b, check_outputs)
- m32r_insn * a;
- m32r_insn * b;
- const int check_outputs;
+ m32r_insn *a;
+ m32r_insn *b;
+ const int check_outputs;
{
- const CGEN_OPINST * a_operands = CGEN_INSN_OPERANDS (a->insn);
- const CGEN_OPINST * b_ops = CGEN_INSN_OPERANDS (b->insn);
+ const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn);
+ const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn);
int a_index;
/* If at least one of the instructions takes no operands, then there is
eg 'nop'. */
if (a_operands == NULL || b_ops == NULL)
return 0;
-
+
/* Scan the operand list of 'a' looking for an output operand. */
for (a_index = 0;
a_operands->type != CGEN_OPINST_END;
if (a_operands->type == CGEN_OPINST_OUTPUT)
{
int b_index;
- const CGEN_OPINST * b_operands = b_ops;
+ const CGEN_OPINST *b_operands = b_ops;
/* Special Case:
The Condition bit 'C' is a shadow of the CBR register (control
register 1) and also a shadow of bit 31 of the program status
word (control register 0). For now this is handled here, rather
- than by cgen.... */
-
+ than by cgen.... */
+
if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
{
/* Scan operand list of 'b' looking for another reference to the
condition bit, which goes in the right direction. */
for (b_index = 0;
b_operands->type != CGEN_OPINST_END;
- b_index ++, b_operands ++)
+ b_index++, b_operands++)
{
if ((b_operands->type
== (check_outputs
right direction. */
for (b_index = 0;
b_operands->type != CGEN_OPINST_END;
- b_index ++, b_operands ++)
+ b_index++, b_operands++)
{
if ((b_operands->type
== (check_outputs
? CGEN_OPINST_OUTPUT
: CGEN_OPINST_INPUT))
&& (b_operands->hw_type == a_operands->hw_type)
- && (a->indices [a_index] == b->indices [b_index]))
+ && (a->indices[a_index] == b->indices[b_index]))
return 1;
}
}
static int
writes_to_pc (a)
- m32r_insn * a;
+ m32r_insn *a;
{
-#if 0 /* Once PC operands are working.... */
- const CGEN_OPINST * a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc,
- a->insn);
+#if 0
+ /* Once PC operands are working.... */
+ const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc,
+ a->insn);
if (a_operands == NULL)
return 0;
while (a_operands->type != CGEN_OPINST_END)
{
if (a_operands->operand != NULL
- && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, a_operands->operand) == M32R_OPERAND_PC)
+ && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc,
+ a_operands->operand) == M32R_OPERAND_PC)
return 1;
-
- a_operands ++;
+
+ a_operands++;
}
#else
if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
return 0;
}
-/* Returns NULL if the two 16 bit insns can be executed in parallel,
- otherwise it returns a pointer to an error message explaining why not. */
+/* Return NULL if the two 16 bit insns can be executed in parallel.
+ Otherwise return a pointer to an error message explaining why not. */
static const char *
can_make_parallel (a, b)
- m32r_insn * a;
- m32r_insn * b;
+ m32r_insn *a;
+ m32r_insn *b;
{
PIPE_ATTR a_pipe;
PIPE_ATTR b_pipe;
-
+
/* Make sure the instructions are the right length. */
- if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
- || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
- abort();
+ if (CGEN_FIELDS_BITSIZE (&a->fields) != 16
+ || CGEN_FIELDS_BITSIZE (&b->fields) != 16)
+ abort ();
if (first_writes_to_seconds_operands (a, b, true))
return _("Instructions write to the same destination register.");
-
+
a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE);
/* Make sure that the instructions use the correct execution pipelines. */
- if ( a_pipe == PIPE_NONE
+ if (a_pipe == PIPE_NONE
|| b_pipe == PIPE_NONE)
return _("Instructions do not use parallel execution pipelines.");
/* Leave this test for last, since it is the only test that can
go away if the instructions are swapped, and we want to make
sure that any other errors are detected before this happens. */
- if ( a_pipe == PIPE_S
+ if (a_pipe == PIPE_S
|| b_pipe == PIPE_O)
return _("Instructions share the same execution pipeline");
-
+
return NULL;
}
#if CGEN_INT_INSN_P
*buffer |= 0x8000;
#else
- buffer [CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
+ buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
|= 0x80;
#endif
}
target_make_parallel (buffer)
char *buffer;
{
- buffer [CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
+ buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
|= 0x80;
}
static void
assemble_two_insns (str, str2, parallel_p)
- char * str;
- char * str2;
- int parallel_p;
+ char *str;
+ char *str2;
+ int parallel_p;
{
- char * str3;
+ char *str3;
m32r_insn first;
m32r_insn second;
- char * errmsg;
- char save_str2 = *str2;
+ char *errmsg;
+ char save_str2 = *str2;
- * str2 = 0; /* Seperate the two instructions. */
+ /* Seperate the two instructions. */
+ *str2 = 0;
/* Make sure the two insns begin on a 32 bit boundary.
This is also done for the serial case (foo -> bar), relaxing doesn't
fill_insn (0);
first.debug_sym_link = debug_sym_link;
- debug_sym_link = (sym_linkS *)0;
+ debug_sym_link = (sym_linkS *) 0;
/* Parse the first instruction. */
if (! (first.insn = m32r_cgen_assemble_insn
/* Check it. */
if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("not a 16 bit instruction '%s'"), str);
return;
}
else if (! enable_special
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
return;
}
else if (! enable_m32rx
- /* FIXME: Need standard macro to perform this test. */
- && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
+ /* FIXME: Need standard macro to perform this test. */
+ && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
+ == (1 << MACH_M32RX)))
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("instruction '%s' is for the M32RX only"), str);
return;
}
-
+
/* Check to see if this is an allowable parallel insn. */
- if (parallel_p && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
+ if (parallel_p
+ && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("instruction '%s' cannot be executed in parallel."), str);
return;
}
-
- *str2 = save_str2; /* Restore the original assembly text, just in case it is needed. */
- str3 = str; /* Save the original string pointer. */
- str = str2 + 2; /* Advanced past the parsed string. */
- str2 = str3; /* Remember the entire string in case it is needed for error messages. */
+
+ /* Restore the original assembly text, just in case it is needed. */
+ *str2 = save_str2;
+
+ /* Save the original string pointer. */
+ str3 = str;
+
+ /* Advanced past the parsed string. */
+ str = str2 + 2;
+
+ /* Remember the entire string in case it is needed for error
+ messages. */
+ str2 = str3;
/* Convert the opcode to lower case. */
{
char *s2 = str;
-
- while (isspace (*s2 ++))
+
+ while (isspace (*s2++))
continue;
--s2;
{
if (isupper ((unsigned char) *s2))
*s2 = tolower (*s2);
- s2 ++;
+ s2++;
}
}
-
- /* Preserve any fixups that have been generated and reset the list to empty. */
+
+ /* Preserve any fixups that have been generated and reset the list
+ to empty. */
gas_cgen_save_fixups ();
/* Get the indices of the operands of the instruction. */
(gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16,
first.indices, &tmp_fields);
}
-
+
if (first.insn == NULL)
as_fatal (_("internal error: lookup/get operands failed"));
/* Check it. */
if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("not a 16 bit instruction '%s'"), str);
return;
}
else if (! enable_special
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
return;
}
else if (! enable_m32rx
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("instruction '%s' is for the M32RX only"), str);
return;
}
/* Check to see if this is an allowable parallel insn. */
- if (parallel_p && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
+ if (parallel_p
+ && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("instruction '%s' cannot be executed in parallel."), str);
return;
}
-
+
if (parallel_p && ! enable_m32rx)
{
if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
&& CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
return;
}
(gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16,
second.indices, &tmp_fields);
}
-
+
if (second.insn == NULL)
as_fatal (_("internal error: lookup/get operands failed"));
variable warn_explicit_parallel_conflicts is true then we do generate
a warning message. Similarly we assume that parallel branch and jump
instructions are deliberate and should not produce errors. */
-
+
if (parallel_p && warn_explicit_parallel_conflicts)
{
- if (first_writes_to_seconds_operands (& first, & second, false))
- /* xgettext:c-format */
+ if (first_writes_to_seconds_operands (&first, &second, false))
+ /* xgettext:c-format */
as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
-
- if (first_writes_to_seconds_operands (& second, & first, false))
- /* xgettext:c-format */
+
+ if (first_writes_to_seconds_operands (&second, &first, false))
+ /* xgettext:c-format */
as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
}
-
+
if (!parallel_p
- || (errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
+ || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL)
{
/* Get the fixups for the first instruction. */
gas_cgen_swap_fixups ();
/* Write it out. */
expand_debug_syms (first.debug_sym_link, 1);
gas_cgen_finish_insn (first.orig_insn, first.buffer,
- CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
-
+ CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
+
/* Force the top bit of the second insn to be set. */
if (parallel_p)
make_parallel (second.buffer);
/* Write it out. */
expand_debug_syms (second.debug_sym_link, 1);
gas_cgen_finish_insn (second.orig_insn, second.buffer,
- CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
+ CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
}
/* Try swapping the instructions to see if they work that way. */
- else if (can_make_parallel (& second, & first) == NULL)
+ else if (can_make_parallel (&second, &first) == NULL)
{
/* Write out the second instruction first. */
expand_debug_syms (second.debug_sym_link, 1);
gas_cgen_finish_insn (second.orig_insn, second.buffer,
- CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
-
+ CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
+
/* Force the top bit of the first instruction to be set. */
make_parallel (first.buffer);
/* Write out the first instruction. */
expand_debug_syms (first.debug_sym_link, 1);
gas_cgen_finish_insn (first.orig_insn, first.buffer,
- CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
+ CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
}
else
{
as_bad ("'%s': %s", str2, errmsg);
return;
}
-
+
/* Set these so m32r_fill_insn can use them. */
prev_seg = now_seg;
prev_subseg = now_subseg;
void
md_assemble (str)
- char * str;
+ char *str;
{
m32r_insn insn;
- char * errmsg;
- char * str2 = NULL;
+ char *errmsg;
+ char *str2 = NULL;
/* Initialize GAS's cgen interface for a new instruction. */
gas_cgen_init_parse ();
assemble_two_insns (str, str2, 0);
return;
}
-
+
insn.debug_sym_link = debug_sym_link;
- debug_sym_link = (sym_linkS *)0;
+ debug_sym_link = (sym_linkS *) 0;
insn.insn = m32r_cgen_assemble_insn
- (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
-
+ (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg);
+
if (!insn.insn)
{
as_bad (errmsg);
if (! enable_special
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
return;
}
else if (! enable_m32rx
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("instruction '%s' is for the M32RX only"), str);
return;
}
-
+
if (CGEN_INSN_BITSIZE (insn.insn) == 32)
{
/* 32 bit insns must live on 32 bit boundaries. */
/* Doesn't really matter what we pass for RELAX_P here. */
gas_cgen_finish_insn (insn.insn, insn.buffer,
- CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
+ CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL);
}
else
{
int swap = false;
if (CGEN_INSN_BITSIZE (insn.insn) != 16)
- abort();
+ abort ();
insn.orig_insn = insn.insn;
boundary. */
if (prev_insn.insn && seen_relaxable_p && optimize)
fill_insn (0);
-
+
if (enable_m32rx)
{
/* Get the indices of the operands of the instruction.
(gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL,
16, insn.indices, &tmp_fields);
}
-
+
if (insn.insn == NULL)
as_fatal (_("internal error: lookup/get operands failed"));
}
input to the current instruction then it cannot be combined.
Otherwise call can_make_parallel() with both orderings of the
instructions to see if they can be combined. */
- if ( ! on_32bit_boundary_p
- && enable_m32rx
- && optimize
- && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
- && ! writes_to_pc (& prev_insn)
- && ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
- )
+ if (! on_32bit_boundary_p
+ && enable_m32rx
+ && optimize
+ && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
+ && ! writes_to_pc (&prev_insn)
+ && ! first_writes_to_seconds_operands (&prev_insn, &insn, false))
{
- if (can_make_parallel (& prev_insn, & insn) == NULL)
+ if (can_make_parallel (&prev_insn, &insn) == NULL)
make_parallel (insn.buffer);
- else if (can_make_parallel (& insn, & prev_insn) == NULL)
+ else if (can_make_parallel (&insn, &prev_insn) == NULL)
swap = true;
}
frag_grow (4);
gas_cgen_finish_insn (insn.orig_insn, insn.buffer,
- CGEN_FIELDS_BITSIZE (& insn.fields),
- 1 /*relax_p*/, &fi);
+ CGEN_FIELDS_BITSIZE (&insn.fields),
+ 1 /* relax_p */, &fi);
insn.addr = fi.addr;
insn.frag = fi.frag;
insn.num_fixups = fi.num_fixups;
if (swap)
{
- int i,tmp;
+ int i, tmp;
#define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
/* Swap the two insns */
- SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
- SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
+ SWAP_BYTES (prev_insn.addr[0], insn.addr[0]);
+ SWAP_BYTES (prev_insn.addr[1], insn.addr[1]);
target_make_parallel (insn.addr);
prev_insn = insn;
else
prev_insn.insn = NULL;
-
+
/* If the insn needs the following one to be on a 32 bit boundary
(e.g. subroutine calls), fill this insn's slot. */
if (on_32bit_boundary_p
/* The syntax in the manual says constants begin with '#'.
We just ignore it. */
-void
+void
md_operand (expressionP)
- expressionS * expressionP;
+ expressionS *expressionP;
{
- if (* input_line_pointer == '#')
+ if (*input_line_pointer == '#')
{
- input_line_pointer ++;
+ input_line_pointer++;
expression (expressionP);
}
}
valueT
md_section_align (segment, size)
- segT segment;
+ segT segment;
valueT size;
{
int align = bfd_get_section_alignment (stdoutput, segment);
symbolS *
md_undefined_symbol (name)
- char * name;
+ char *name;
{
return 0;
}
/* .scomm pseudo-op handler.
This is a new pseudo-op to handle putting objects in .scommon.
- By doing this the linker won't need to do any work and more importantly
- it removes the implicit -G arg necessary to correctly link the object file.
-*/
+ By doing this the linker won't need to do any work,
+ and more importantly it removes the implicit -G arg necessary to
+ correctly link the object file. */
static void
m32r_scomm (ignore)
int ignore;
{
- register char * name;
- register char c;
- register char * p;
- offsetT size;
- register symbolS * symbolP;
- offsetT align;
- int align2;
+ register char *name;
+ register char c;
+ register char *p;
+ offsetT size;
+ register symbolS *symbolP;
+ offsetT align;
+ int align2;
name = input_line_pointer;
c = get_symbol_end ();
- /* just after name is now '\0' */
+ /* Just after name is now '\0'. */
p = input_line_pointer;
- * p = c;
+ *p = c;
SKIP_WHITESPACE ();
- if (* input_line_pointer != ',')
+ if (*input_line_pointer != ',')
{
as_bad (_("Expected comma after symbol-name: rest of line ignored."));
ignore_rest_of_line ();
return;
}
- input_line_pointer ++; /* skip ',' */
+ /* Skip ','. */
+ input_line_pointer++;
if ((size = get_absolute_expression ()) < 0)
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
ignore_rest_of_line ();
return;
}
/* The third argument to .scomm is the alignment. */
- if (* input_line_pointer != ',')
+ if (*input_line_pointer != ',')
align = 8;
else
{
- ++ input_line_pointer;
+ ++input_line_pointer;
align = get_absolute_expression ();
if (align <= 0)
{
align = 8;
}
}
+
/* Convert to a power of 2 alignment. */
if (align)
{
- for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
+ for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
continue;
if (align != 1)
{
else
align2 = 0;
- * p = 0;
+ *p = 0;
symbolP = symbol_find_or_make (name);
- * p = c;
+ *p = c;
if (S_IS_DEFINED (symbolP))
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("Ignoring attempt to re-define symbol `%s'."),
S_GET_NAME (symbolP));
ignore_rest_of_line ();
if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
{
- /* xgettext:c-format */
+ /* xgettext:c-format */
as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
S_GET_NAME (symbolP),
(long) S_GET_VALUE (symbolP),
if (symbol_get_obj (symbolP)->local)
{
- segT old_sec = now_seg;
- int old_subsec = now_subseg;
- char * pfrag;
+ segT old_sec = now_seg;
+ int old_subsec = now_subseg;
+ char *pfrag;
record_alignment (sbss_section, align2);
subseg_set (sbss_section, 0);
-
+
if (align2)
frag_align (align2, 0, 0);
-
+
if (S_GET_SEGMENT (symbolP) == sbss_section)
symbol_get_frag (symbolP)->fr_symbol = 0;
-
+
symbol_set_frag (symbolP, frag_now);
-
+
pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
(char *) 0);
- * pfrag = 0;
+ *pfrag = 0;
S_SET_SIZE (symbolP, size);
S_SET_SEGMENT (symbolP, sbss_section);
S_CLEAR_EXTERNAL (symbolP);
S_SET_VALUE (symbolP, (valueT) size);
S_SET_ALIGN (symbolP, align2);
S_SET_EXTERNAL (symbolP);
- S_SET_SEGMENT (symbolP, & scom_section);
+ S_SET_SEGMENT (symbolP, &scom_section);
}
demand_empty_rest_of_line ();
long
m32r_relax_frag (fragP, stretch)
- fragS * fragP;
- long stretch;
+ fragS *fragP;
+ long stretch;
{
/* Address of branch insn. */
long address = fragP->fr_address + fragP->fr_fix - 2;
Any symbol that is now undefined will not become defined.
The guess for fr_var is ACTUALLY the growth beyond fr_fix.
Whatever we do to grow fr_fix or fr_var contributes to our returned value.
- Although it may not be explicit in the frag, pretend fr_var starts with a
- 0 value. */
+ Although it may not be explicit in the frag, pretend fr_var starts
+ with a 0 value. */
int
md_estimate_size_before_relax (fragP, segment)
- fragS * fragP;
- segT segment;
+ fragS *fragP;
+ segT segment;
{
- int old_fr_fix = fragP->fr_fix;
+ int old_fr_fix = fragP->fr_fix;
/* The only thing we have to handle here are symbols outside of the
current segment. They may be undefined or in a different segment in
all further handling to md_convert_frag. */
fragP->fr_subtype = 2;
-#if 0 /* Can't use this, but leave in for illustration. */
+#if 0
+ /* Can't use this, but leave in for illustration. */
/* Change 16 bit insn to 32 bit insn. */
fragP->fr_opcode[0] |= 0x80;
/* Create a relocation for it. */
fix_new (fragP, old_fr_fix, 4,
fragP->fr_symbol,
- fragP->fr_offset, 1 /* pcrel */,
+ fragP->fr_offset, 1 /* pcrel */,
/* FIXME: Can't use a real BFD reloc here.
gas_cgen_md_apply_fix3 can't handle it. */
BFD_RELOC_M32R_26_PCREL);
frag_wane (fragP);
#else
{
- const CGEN_INSN * insn;
- int i;
+ const CGEN_INSN *insn;
+ int i;
/* Update the recorded insn.
Fortunately we don't have to look very far.
}
return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
-}
+}
-/* *fragP has been relaxed to its final size, and now needs to have
+/* *FRAGP has been relaxed to its final size, and now needs to have
the bytes inside it modified to conform to the new size.
Called after relaxation is finished.
void
md_convert_frag (abfd, sec, fragP)
- bfd * abfd;
- segT sec;
- fragS * fragP;
+ bfd *abfd;
+ segT sec;
+ fragS *fragP;
{
- char * opcode;
- char * displacement;
- int target_address;
- int opcode_address;
- int extension;
- int addend;
+ char *opcode;
+ char *displacement;
+ int target_address;
+ int opcode_address;
+ int extension;
+ int addend;
opcode = fragP->fr_opcode;
switch (fragP->fr_subtype)
{
- case 1 :
+ case 1:
extension = 0;
- displacement = & opcode[1];
+ displacement = &opcode[1];
break;
- case 2 :
+ case 2:
opcode[0] |= 0x80;
extension = 2;
- displacement = & opcode[1];
+ displacement = &opcode[1];
break;
- case 3 :
+ case 3:
opcode[2] = opcode[0] | 0x80;
md_number_to_chars (opcode, PAR_NOP_INSN, 2);
opcode_address += 2;
extension = 4;
- displacement = & opcode[3];
+ displacement = &opcode[3];
break;
- default :
+ default:
abort ();
}
if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
{
- /* symbol must be resolved by linker */
+ /* Symbol must be resolved by linker. */
if (fragP->fr_offset & 3)
as_warn (_("Addend to unresolved symbol not on word boundary."));
addend = fragP->fr_offset >> 2;
/* Offset of branch insn in frag. */
fragP->fr_fix + extension - 4,
fragP->fr_cgen.insn,
- 4 /*length*/,
- /* FIXME: quick hack */
+ 4 /* Length. */,
+ /* FIXME: quick hack. */
#if 0
cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
fragP->fr_cgen.opindex),
long
md_pcrel_from_section (fixP, sec)
- fixS * fixP;
- segT sec;
+ fixS *fixP;
+ segT sec;
{
if (fixP->fx_addsy != (symbolS *) NULL
&& (! S_IS_DEFINED (fixP->fx_addsy)
bfd_reloc_code_real_type
md_cgen_lookup_reloc (insn, operand, fixP)
- const CGEN_INSN * insn;
- const CGEN_OPERAND * operand;
- fixS * fixP;
+ const CGEN_INSN *insn;
+ const CGEN_OPERAND *operand;
+ fixS *fixP;
{
switch (operand->type)
{
- case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
- case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
- case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
- case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
- case M32R_OPERAND_HI16 :
- case M32R_OPERAND_SLO16 :
- case M32R_OPERAND_ULO16 :
+ case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL;
+ case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL;
+ case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL;
+ case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24;
+ case M32R_OPERAND_HI16:
+ case M32R_OPERAND_SLO16:
+ case M32R_OPERAND_ULO16:
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
if (fixP->fx_cgen.opinfo != 0)
return fixP->fx_cgen.opinfo;
break;
- default : /* avoid -Wall warning */
+ default:
+ /* Avoid -Wall warning. */
break;
}
return BFD_RELOC_NONE;
static void
m32r_record_hi16 (reloc_type, fixP, seg)
- int reloc_type;
- fixS * fixP;
- segT seg;
+ int reloc_type;
+ fixS *fixP;
+ segT seg;
{
- struct m32r_hi_fixup * hi_fixup;
+ struct m32r_hi_fixup *hi_fixup;
assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
|| reloc_type == BFD_RELOC_M32R_HI16_ULO);
hi_fixup->fixp = fixP;
hi_fixup->seg = now_seg;
hi_fixup->next = m32r_hi_fixup_list;
-
+
m32r_hi_fixup_list = hi_fixup;
}
fixS *
m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
- fragS * frag;
- int where;
- const CGEN_INSN * insn;
- int length;
- const CGEN_OPERAND * operand;
- int opinfo;
- expressionS * exp;
+ fragS *frag;
+ int where;
+ const CGEN_INSN *insn;
+ int length;
+ const CGEN_OPERAND *operand;
+ int opinfo;
+ expressionS *exp;
{
- fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
- operand, opinfo, exp);
+ fixS *fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
+ operand, opinfo, exp);
switch (operand->type)
{
- case M32R_OPERAND_HI16 :
+ case M32R_OPERAND_HI16:
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO
|| fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
break;
- default : /* avoid -Wall warning */
+ default:
+ /* Avoid -Wall warning */
break;
}
void
m32r_frob_file ()
{
- struct m32r_hi_fixup * l;
+ struct m32r_hi_fixup *l;
for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
{
- segment_info_type * seginfo;
- int pass;
+ segment_info_type *seginfo;
+ int pass;
assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
|| FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
seginfo = seg_info (l->seg);
for (pass = 0; pass < 2; pass++)
{
- fixS * f;
- fixS * prev;
+ fixS *f;
+ fixS *prev;
prev = NULL;
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|| (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
&& FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
|| prev->fx_addsy != f->fx_addsy
- || prev->fx_offset != f->fx_offset))
+ || prev->fx_offset != f->fx_offset))
{
- fixS ** pf;
+ fixS **pf;
/* Move l->fixp before f. */
for (pf = &seginfo->fix_root;
- * pf != l->fixp;
- pf = & (* pf)->fx_next)
- assert (* pf != NULL);
+ *pf != l->fixp;
+ pf = & (*pf)->fx_next)
+ assert (*pf != NULL);
- * pf = l->fixp->fx_next;
+ *pf = l->fixp->fx_next;
l->fixp->fx_next = f;
if (prev == NULL)
int
m32r_force_relocation (fix)
- fixS * fix;
+ fixS *fix;
{
if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
if (! m32r_relax)
return 0;
- return (fix->fx_pcrel
- || 0 /* ??? */);
+ return fix->fx_pcrel;
}
\f
/* Write a value out to the object file, using the appropriate endianness. */
void
md_number_to_chars (buf, val, n)
- char * buf;
+ char *buf;
valueT val;
- int n;
+ int n;
{
if (target_big_endian)
number_to_chars_bigendian (buf, val, n);
number_to_chars_littleendian (buf, val, n);
}
-/* Turn a string in input_line_pointer into a floating point constant of type
- type, and store the appropriate bytes in *litP. The number of LITTLENUMS
- emitted is stored in *sizeP . An error message is returned, or NULL on OK.
-*/
+/* Turn a string in input_line_pointer into a floating point constant
+ of type TYPE, and store the appropriate bytes in *LITP. The number
+ of LITTLENUMS emitted is stored in *SIZEP. An error message is
+ returned, or NULL on OK. */
-/* Equal to MAX_PRECISION in atof-ieee.c */
+/* Equal to MAX_PRECISION in atof-ieee.c. */
#define MAX_LITTLENUMS 6
char *
char *litP;
int *sizeP;
{
- int i;
- int prec;
- LITTLENUM_TYPE words [MAX_LITTLENUMS];
- char * t;
- char * atof_ieee ();
+ int i;
+ int prec;
+ LITTLENUM_TYPE words[MAX_LITTLENUMS];
+ char *t;
+ char *atof_ieee ();
switch (type)
{
prec = 4;
break;
- /* FIXME: Some targets allow other format chars for bigger sizes here. */
+ /* FIXME: Some targets allow other format chars for bigger sizes
+ here. */
default:
- * sizeP = 0;
+ *sizeP = 0;
return _("Bad call to md_atof()");
}
t = atof_ieee (input_line_pointer, type, words);
if (t)
input_line_pointer = t;
- * sizeP = prec * sizeof (LITTLENUM_TYPE);
+ *sizeP = prec * sizeof (LITTLENUM_TYPE);
if (target_big_endian)
{
litP += sizeof (LITTLENUM_TYPE);
}
}
-
+
return 0;
}
/* If we have reached the end of a section and we have just emitted a
16 bit insn, then emit a nop to make sure that the section ends on
a 32 bit boundary. */
-
+
if (prev_insn.insn || seen_relaxable_p)
(void) m32r_fill_insn (0);
}
/* Return true if can adjust the reloc to be relative to its section
- (such as .data) instead of relative to some symbol. */
+ (such as .data) instead of relative to some symbol. */
boolean
m32r_fix_adjustable (fixP)
{
bfd_reloc_code_real_type reloc_type;
-
+
if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
{
const CGEN_INSN *insn = NULL;
int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
- const CGEN_OPERAND *operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
+ const CGEN_OPERAND *operand =
+ cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
}
else
if (fixP->fx_addsy == NULL)
return 1;
- /* Prevent all adjustments to global symbols. */
+ /* Prevent all adjustments to global symbols. */
if (S_IS_EXTERN (fixP->fx_addsy))
return 0;
if (S_IS_WEAK (fixP->fx_addsy))
return 0;
- /* We need the symbol name for the VTABLE entries */
+ /* We need the symbol name for the VTABLE entries. */
if (reloc_type == BFD_RELOC_VTABLE_INHERIT
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
projects / deliverable / binutils-gdb.git / commitdiff
