ARM: tegra: don't unlock MMIO access to DBGLAR

There is no need to unlock MMIO access to the DBGLAR all the time. Doing
so may even cause problems if a SW bug causes writes to that MMIO region.

Cortex-A15 processors do not support the CP14 register write the code
currently uses to unlock the DBGLAR; the instruction throws an undefined
instruction exceptions. This prevents tegra_secondary_startup() from
executing on Tegra114, and hence prevents SMP.

Remove the code that unlocks this access.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fd473f2b4c3d981e391a3fd8560c51f0b3ddedce..045c16f2dd51fae9d86551d91cb883f6e5d03aba 100644 (file)
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,8 +7,5 @@
 
 ENTRY(tegra_secondary_startup)
         bl      v7_invalidate_l1
-       /* Enable coresight */
-       mov32   r0, 0xC5ACCE55
-       mcr     p14, 0, r0, c7, c12, 6
         b       secondary_startup
 ENDPROC(tegra_secondary_startup)

diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index ff7b45c6c2a0ae114ac90a8fc19a606d90e6cf0e..1676aba5e7b84ecf97c577b2ccc8d5ff565308dd 100644 (file)
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -41,9 +41,6 @@
  */
 ENTRY(tegra_resume)
        bl      v7_invalidate_l1
-       /* Enable coresight */
-       mov32   r0, 0xC5ACCE55
-       mcr     p14, 0, r0, c7, c12, 6
 
        cpu_id  r0
        cmp     r0, #0                          @ CPU0?