ath9k: Program AR_WA correctly
authorSujith Manoharan <c_manoha@qca.qualcomm.com>
Mon, 2 Feb 2015 12:51:11 +0000 (18:21 +0530)
committerKalle Valo <kvalo@codeaurora.org>
Fri, 6 Feb 2015 06:39:32 +0000 (08:39 +0200)
Setting the required configuration in the PCIE
WorkAround register needs to be done after all the
WoW parameters have been set.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
drivers/net/wireless/ath/ath9k/ar9003_wow.c

index 6ffa0e0d028c905dbb42b6a5c70049c3fdc43c77..cf45b91f0a60084c908db01a906f32bbeef74b65 100644 (file)
@@ -219,30 +219,33 @@ u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
 
+static void ath9k_hw_wow_set_arwr_reg(struct ath_hw *ah)
+{
+       u32 wa_reg;
+
+       if (!ah->is_pciexpress)
+               return;
+
+       /*
+        * We need to untie the internal POR (power-on-reset)
+        * to the external PCI-E reset. We also need to tie
+        * the PCI-E Phy reset to the PCI-E reset.
+        */
+       wa_reg = REG_READ(ah, AR_WA);
+       wa_reg &= ~AR_WA_UNTIE_RESET_EN;
+       wa_reg |= AR_WA_RESET_EN;
+       wa_reg |= AR_WA_POR_SHORT;
+
+       REG_WRITE(ah, AR_WA, wa_reg);
+}
+
 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
 {
        u32 wow_event_mask;
        u32 keep_alive, magic_pattern, host_pm_ctrl;
-       u32 set, clr;
 
        wow_event_mask = ah->wow.wow_event_mask;
 
-       /*
-        * Untie Power-on-Reset from the PCI-E-Reset. When we are in
-        * WOW sleep, we do want the Reset from the PCI-E to disturb
-        * our hw state
-        */
-       if (ah->is_pciexpress) {
-               /*
-                * we need to untie the internal POR (power-on-reset)
-                * to the external PCI-E reset. We also need to tie
-                * the PCI-E Phy reset to the PCI-E reset.
-                */
-               set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
-               clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
-               REG_RMW(ah, AR_WA, set, clr);
-       }
-
        /*
         * AR_PMCTRL_HOST_PME_EN - Override PME enable in configuration
         *                         space and allow MAC to generate WoW anyway.
@@ -390,6 +393,8 @@ void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
        /* To bring down WOW power low margin */
        REG_SET_BIT(ah, AR_PCIE_PHY_REG3, BIT(13));
 
+       ath9k_hw_wow_set_arwr_reg(ah);
+
        /* HW WoW */
        REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, BIT(5));
 
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