* mn10300_sim.h (struct _state): Put all registers into a single

        array to make gdb implementation easier.
        (REG_*): Add definitions for all registers in the state array.
        (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
        * simops.c: Related changes.

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index 634b5f9da675cfa04917803c5aa16f005ad940b3..9f8831073ba254d847f2131fcf7368ba3f2fe945 100644 (file)
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,3 +1,11 @@
+Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * mn10300_sim.h (struct _state): Put all registers into a single
+       array to make gdb implementation easier.
+       (REG_*): Add definitions for all registers in the state array.
+       (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
+       * simops.c: Related changes.
+
 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
 
        * interp.c (sim_resume): Handle 0xff as a single byte insn.

diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300_sim.h
index abeaa4348b96664ac104ab745d38ca2b2ae9c774..f0913f3db8600ad51e4cde428c56fcffe52ba4cf 100644 (file)
--- a/sim/mn10300/mn10300_sim.h
+++ b/sim/mn10300/mn10300_sim.h
@@ -51,6 +51,7 @@ struct simops
   long mask;
   void (*func)();
   int length;
+  int format;
   int numops;
   int operands[16];
 };
@@ -59,9 +60,8 @@ struct simops
 
 struct _state
 {
-  reg_t regs[12];              /* registers, d0-d3, a0-a3, sp, mdr, lar, lir */
-  reg_t sregs[8];              /* system registers, including psw */
-  reg_t pc;
+  reg_t regs[12];              /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
+                                  lir, lar */
   uint8 *mem;                  /* main memory */
   int exception;
 } State;
@@ -69,9 +69,9 @@ struct _state
 extern uint32 OP[4];
 extern struct simops Simops[];
 
-#define PC     (State.pc)
+#define PC     (State.regs[9])
 
-#define PSW (State.sregs[0])
+#define PSW (State.regs[11])
 #define PSW_V 0x1
 #define PSW_C 0x2
 #define PSW_N 0x4
@@ -80,9 +80,11 @@ extern struct simops Simops[];
 #define REG_D0 0
 #define REG_A0 4
 #define REG_SP 8
-#define REG_MDR 9
-#define REG_LAR 10
-#define REG_LIR 11
+#define REG_PC 9
+#define REG_MDR 10
+#define REG_PSW 11
+#define REG_LIR 12
+#define REG_LAR 13
 
 #define SEXT3(x)       ((((x)&0x7)^(~0x3))+0x4)        
 
@@ -104,18 +106,6 @@ extern struct simops Simops[];
 /* sign-extend a 22-bit number */
 #define SEXT22(x)      ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 
-/* sign-extend a 32-bit number */
-#define SEXT32(x)      ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL)
-
-/* sign extend a 40 bit number */
-#define SEXT40(x)      ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
-
-/* sign extend a 44 bit number */
-#define SEXT44(x)      ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL)
-
-/* sign extend a 60 bit number */
-#define SEXT60(x)      ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL)
-
 #define MAX32  0x7fffffffLL
 #define MIN32  0xff80000000LL
 #define MASK32 0xffffffffLL

diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index 719aaf573279e21b0d95f3d1e1e7574b0915dc0d..56298458f4a81c51a91cbb81ec5d96ceaa5422d4 100644 (file)
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -2253,7 +2253,7 @@ void OP_C800 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (PSW & PSW_Z)
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bne label:8 */
@@ -2263,7 +2263,7 @@ void OP_C900 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (!(PSW & PSW_Z))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bgt label:8 */
@@ -2274,7 +2274,7 @@ void OP_C100 (insn, extension)
      we subtract two here to make things right.  */
   if (!((PSW & PSW_Z)
         || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bge label:8 */
@@ -2284,7 +2284,7 @@ void OP_C200 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* ble label:8 */
@@ -2295,7 +2295,7 @@ void OP_C300 (insn, extension)
      we subtract two here to make things right.  */
   if ((PSW & PSW_Z)
        || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* blt label:8 */
@@ -2305,7 +2305,7 @@ void OP_C000 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bhi label:8 */
@@ -2315,7 +2315,7 @@ void OP_C500 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bcc label:8 */
@@ -2325,7 +2325,7 @@ void OP_C600 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (!(PSW & PSW_C))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bls label:8 */
@@ -2335,7 +2335,7 @@ void OP_C700 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bcs label:8 */
@@ -2345,7 +2345,7 @@ void OP_C400 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (PSW & PSW_C)
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bvc label:8 */
@@ -2355,7 +2355,7 @@ void OP_F8E800 (insn, extension)
   /* The dispatching code will add 3 after we return, so
      we subtract two here to make things right.  */
   if (!(PSW & PSW_V))
-    State.pc += SEXT8 (insn & 0xff) - 3;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
 }
 
 /* bvs label:8 */
@@ -2365,7 +2365,7 @@ void OP_F8E900 (insn, extension)
   /* The dispatching code will add 3 after we return, so
      we subtract two here to make things right.  */
   if (PSW & PSW_V)
-    State.pc += SEXT8 (insn & 0xff) - 3;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
 }
 
 /* bnc label:8 */
@@ -2375,7 +2375,7 @@ void OP_F8EA00 (insn, extension)
   /* The dispatching code will add 3 after we return, so
      we subtract two here to make things right.  */
   if (!(PSW & PSW_N))
-    State.pc += SEXT8 (insn & 0xff) - 3;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
 }
 
 /* bns label:8 */
@@ -2385,7 +2385,7 @@ void OP_F8EB00 (insn, extension)
   /* The dispatching code will add 3 after we return, so
      we subtract two here to make things right.  */
   if (PSW & PSW_N)
-    State.pc += SEXT8 (insn & 0xff) - 3;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
 }
 
 /* bra label:8 */
@@ -2394,7 +2394,7 @@ void OP_CA00 (insn, extension)
 {
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
-  State.pc += SEXT8 (insn & 0xff) - 2;
+  State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* leq */
@@ -2485,21 +2485,21 @@ void OP_DB (insn, extension)
 void OP_F0F4 (insn, extension)
      unsigned long insn, extension;
 {
-  State.pc = State.regs[REG_A0 + REG0 (insn)] - 2;
+  State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
 }
 
 /* jmp label:16 */
 void OP_CC0000 (insn, extension)
      unsigned long insn, extension;
 {
-  State.pc += SEXT16 (insn & 0xffff) - 3;
+  State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3;
 }
 
 /* jmp label:32 */
 void OP_DC000000 (insn, extension)
      unsigned long insn, extension;
 {
-  State.pc += (((insn & 0xffffff) << 8) + extension) - 5;
+  State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5;
 }
 
 /* call label:16,reg_list,imm8 */
@@ -2510,7 +2510,7 @@ void OP_CD000000 (insn, extension)
   unsigned long mask;
 
   sp = State.regs[REG_SP];
-  next_pc = State.pc + 2;
+  next_pc = State.regs[REG_PC] + 2;
   State.mem[sp] = next_pc & 0xff;
   State.mem[sp+1] = (next_pc & 0xff00) >> 8;
   State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
@@ -2565,7 +2565,7 @@ void OP_CD000000 (insn, extension)
   /* And make sure to update the stack pointer.  */
   State.regs[REG_SP] -= extension;
   State.regs[REG_MDR] = next_pc;
-  State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
+  State.regs[REG_PC] += SEXT16 ((insn & 0xffff00) >> 8) - 5;
 }
 
 /* call label:32,reg_list,imm8*/
@@ -2576,7 +2576,7 @@ void OP_DD000000 (insn, extension)
   unsigned long mask;
 
   sp = State.regs[REG_SP];
-  next_pc = State.pc + 2;
+  next_pc = State.regs[REG_PC] + 2;
   State.mem[sp] = next_pc & 0xff;
   State.mem[sp+1] = (next_pc & 0xff00) >> 8;
   State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
@@ -2631,7 +2631,7 @@ void OP_DD000000 (insn, extension)
   /* And make sure to update the stack pointer.  */
   State.regs[REG_SP] -= (extension & 0xff);
   State.regs[REG_MDR] = next_pc;
-  State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
+  State.regs[REG_PC] += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
 }
 
 /* calls (an) */
@@ -2641,13 +2641,13 @@ void OP_F0F0 (insn, extension)
   unsigned int next_pc, sp;
 
   sp = State.regs[REG_SP];
-  next_pc = State.pc + 2;
+  next_pc = State.regs[REG_PC] + 2;
   State.mem[sp] = next_pc & 0xff;
   State.mem[sp+1] = (next_pc & 0xff00) >> 8;
   State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
   State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
   State.regs[REG_MDR] = next_pc;
-  State.pc = State.regs[REG_A0 + REG0 (insn)] - 2;
+  State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
 }
 
 /* calls label:16 */
@@ -2657,13 +2657,13 @@ void OP_FAFF0000 (insn, extension)
   unsigned int next_pc, sp;
 
   sp = State.regs[REG_SP];
-  next_pc = State.pc + 4;
+  next_pc = State.regs[REG_PC] + 4;
   State.mem[sp] = next_pc & 0xff;
   State.mem[sp+1] = (next_pc & 0xff00) >> 8;
   State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
   State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
   State.regs[REG_MDR] = next_pc;
-  State.pc += SEXT16 (insn & 0xffff) - 4;
+  State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 4;
 }
 
 /* calls label:32 */
@@ -2673,13 +2673,13 @@ void OP_FCFF0000 (insn, extension)
   unsigned int next_pc, sp;
 
   sp = State.regs[REG_SP];
-  next_pc = State.pc + 6;
+  next_pc = State.regs[REG_PC] + 6;
   State.mem[sp] = next_pc & 0xff;
   State.mem[sp+1] = (next_pc & 0xff00) >> 8;
   State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
   State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
   State.regs[REG_MDR] = next_pc;
-  State.pc += (((insn & 0xffff) << 16) + extension) - 6;
+  State.regs[REG_PC] += (((insn & 0xffff) << 16) + extension) - 6;
 }
 
 /* ret reg_list, imm8 */
@@ -2741,9 +2741,9 @@ void OP_DF0000 (insn, extension)
   State.regs[REG_SP] = sp;
 
   /* Restore the PC value.  */
-  State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
+  State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
              | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
-  State.pc -= 3;
+  State.regs[REG_PC] -= 3;
 }
 
 /* retf reg_list,imm8 */
@@ -2755,7 +2755,7 @@ void OP_DE0000 (insn, extension)
 
   sp = State.regs[REG_SP] + (insn & 0xff);
   State.regs[REG_SP] = sp;
-  State.pc = State.regs[REG_MDR] - 3;
+  State.regs[REG_PC] = State.regs[REG_MDR] - 3;
 
   sp = State.regs[REG_SP];
 
@@ -2815,9 +2815,9 @@ void OP_F0FC (insn, extension)
   unsigned int sp;
 
   sp = State.regs[REG_SP];
-  State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
+  State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
              | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
-  State.pc -= 2;
+  State.regs[REG_PC] -= 2;
 }
 
 /* rti */