clk: sunxi: add bus gates for A83T
authorVishnu Patekar <vishnupatekar0510@gmail.com>
Sun, 31 Jan 2016 01:20:55 +0000 (09:20 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Tue, 2 Feb 2016 13:14:24 +0000 (14:14 +0100)
A83T has similar bus gates that of H3, including single gating register has
different clock parent.

As per H3 and A83T datasheet, usbhost is under AHB2.

However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.

until, this confusion is cleared keep it H3 way.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Documentation/devicetree/bindings/clock/sunxi.txt
drivers/clk/sunxi/clk-sun8i-bus-gates.c

index 7f19ef55d61f8211e5c141fd9b0fef6670733e1a..c09f59b1747c9c49f8f002e1411a0c8c8b6a67c8 100644 (file)
@@ -58,6 +58,7 @@ Required properties:
        "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
        "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
        "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+       "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
        "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
        "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
        "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
index 1113eb98c9b4f6847378eb979af180aef3abda15..63fdb790df2938ba1f1c35df96020926820ad065 100644 (file)
@@ -109,3 +109,5 @@ err_unmap:
 
 CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
               sun8i_h3_bus_gates_init);
+CLK_OF_DECLARE(sun8i_a83t_bus_gates, "allwinner,sun8i-a83t-bus-gates-clk",
+              sun8i_h3_bus_gates_init);
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