ARM: sun4i: dt: Add pll3 and pll7 clocks

Enable pll3 and pll7 clocks that are needed to drive display clocks.

Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 268a1504d9842143961f75dc8ea40119a5ae378f..a03e56fb5dbc7882abb90fc71298bac1c3e8a56b 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -184,6 +184,15 @@
                        clock-output-names = "osc24M";
                };
 
+               osc3M: osc3M_clk {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clock-div = <8>;
+                       clock-mult = <1>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "osc3M";
+               };
+
                osc32k: clk@0 {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
@@ -208,6 +217,23 @@
                                             "pll2-4x", "pll2-8x";
                };
 
+               pll3: clk@01c20010 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-pll3-clk";
+                       reg = <0x01c20010 0x4>;
+                       clocks = <&osc3M>;
+                       clock-output-names = "pll3";
+               };
+
+               pll3x2: pll3x2_clk {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clock-div = <1>;
+                       clock-mult = <2>;
+                       clocks = <&pll3>;
+                       clock-output-names = "pll3-2x";
+               };
+
                pll4: clk@01c20018 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-pll1-clk";
@@ -232,6 +258,23 @@
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
                };
 
+               pll7: clk@01c20030 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-pll3-clk";
+                       reg = <0x01c20030 0x4>;
+                       clocks = <&osc3M>;
+                       clock-output-names = "pll7";
+               };
+
+               pll7x2: pll7x2_clk {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clock-div = <1>;
+                       clock-mult = <2>;
+                       clocks = <&pll7>;
+                       clock-output-names = "pll7-2x";
+               };
+
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;