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aarch64: Fix MOVPRFX markup for bf16 conversions
authorRichard Sandiford <richard.sandiford@arm.com>
Fri, 31 Jan 2020 08:03:56 +0000 (08:03 +0000)
committerRichard Sandiford <richard.sandiford@arm.com>
Fri, 31 Jan 2020 13:22:46 +0000 (13:22 +0000)
bfcvt converts a .S input to a .H output, so any predicated movprfx
needs to operate on .S rather than .H.  In common with SVE2 narrowing
top operations, bfcvtnt doesn't accept movprfx.

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
Remove C_SCAN_MOVPRFX for SVE bfcvtnt.

gas/
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
.s for the movprfx.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_28.d,
* testsuite/gas/aarch64/sve-movprfx_28.l,
* testsuite/gas/aarch64/sve-movprfx_28.s: New test.

gas/ChangeLog patch | blob | blame | history
gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d patch | blob | blame | history
gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s patch | blob | blame | history
gas/testsuite/gas/aarch64/sve-movprfx_28.d [new file with mode: 0644] patch | blob
gas/testsuite/gas/aarch64/sve-movprfx_28.l [new file with mode: 0644] patch | blob
gas/testsuite/gas/aarch64/sve-movprfx_28.s [new file with mode: 0644] patch | blob
opcodes/ChangeLog patch | blob | blame | history
opcodes/aarch64-tbl.h patch | blob | blame | history

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8bad416a307dec3bcdcb98db614d730d4869f6b8..cff57b095aaa1f271a2833083d111117298476e6 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
+       .s for the movprfx.
+       * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
+       * testsuite/gas/aarch64/sve-movprfx_28.d,
+       * testsuite/gas/aarch64/sve-movprfx_28.l,
+       * testsuite/gas/aarch64/sve-movprfx_28.s: New test.
+
 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 
        * config/tc-i386.c (output_disp): Tighten base_opcode check.
diff --git a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d
index 4ba95b89505e1f84f0cdc5dc522a5252a3a48984..e51bd11427d597b59addec8e0474cb0e4605b925 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d
+++ b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d
@@ -23,5 +23,5 @@ Disassembly of section \.text:
  *[0-9a-f]+:   64e34440        bfmlalt z0\.s, z2\.h, z3\.h\[0\]
  *[0-9a-f]+:   0420bc20        movprfx z0, z1
  *[0-9a-f]+:   658aa040        bfcvt   z0\.h, p0/m, z2\.s
- *[0-9a-f]+:   04512020        movprfx z0\.h, p0/m, z1\.h
+ *[0-9a-f]+:   04912020        movprfx z0\.s, p0/m, z1\.s
  *[0-9a-f]+:   658aa040        bfcvt   z0\.h, p0/m, z2\.s
diff --git a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s
index c322532a80757dd032cf728ef4606af2ab2faaaa..d46da21aac6a59b9073e6118b0eb81bb8738862e 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s
+++ b/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s
@@ -27,5 +27,5 @@ movprfx z0, z1
 bfcvt z0.h, p0/m, z2.s
 
 # Predicated movprfx + bfcvt
-movprfx z0.h, p0/m, z1.h
+movprfx z0.s, p0/m, z1.s
 bfcvt z0.h, p0/m, z2.s
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_28.d b/gas/testsuite/gas/aarch64/sve-movprfx_28.d
new file mode 100644 (file)
index 0000000..808d07d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_28.d
@@ -0,0 +1,31 @@
+#source: sve-movprfx_28.s
+#warning_output: sve-movprfx_28.l
+#as: -I$srcdir/$subdir --generate-missing-build-notes=no
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 04912420        movprfx z0\.s, p1/m, z1\.s
+[^:]+: 658aa440        bfcvt   z0\.h, p1/m, z2\.s
+[^:]+: 04902420        movprfx z0\.s, p1/z, z1\.s
+[^:]+: 658aa440        bfcvt   z0\.h, p1/m, z2\.s
+[^:]+: 04512420        movprfx z0\.h, p1/m, z1\.h
+[^:]+: 658aa440        bfcvt   z0\.h, p1/m, z2\.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+: 04502420        movprfx z0\.h, p1/z, z1\.h
+[^:]+: 658aa440        bfcvt   z0\.h, p1/m, z2\.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+: 0420bc20        movprfx z0, z1
+[^:]+: 658aa440        bfcvt   z0\.h, p1/m, z2\.s
+[^:]+: 0420bc20        movprfx z0, z1
+[^:]+: 648aa440        bfcvtnt z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
+[^:]+: 04912420        movprfx z0\.s, p1/m, z1\.s
+[^:]+: 648aa440        bfcvtnt z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
+[^:]+: 04902420        movprfx z0\.s, p1/z, z1\.s
+[^:]+: 648aa440        bfcvtnt z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
+[^:]+: 04512420        movprfx z0\.h, p1/m, z1\.h
+[^:]+: 648aa440        bfcvtnt z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
+[^:]+: 04502420        movprfx z0\.h, p1/z, z1\.h
+[^:]+: 648aa440        bfcvtnt z0\.h, p1/m, z2\.s  // note: SVE `movprfx' compatible instruction expected
+[^:]+: d65f03c0        ret
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_28.l b/gas/testsuite/gas/aarch64/sve-movprfx_28.l
new file mode 100644 (file)
index 0000000..a75289c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_28.l
@@ -0,0 +1,8 @@
+[^:]*: Assembler messages:
+.*:15: Warning: register size not compatible with previous `movprfx' at operand 1 -- `bfcvt z0.h,p1/m,z2.s'
+.*:19: Warning: register size not compatible with previous `movprfx' at operand 1 -- `bfcvt z0.h,p1/m,z2.s'
+.*:27: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
+.*:31: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
+.*:35: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
+.*:39: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
+.*:43: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_28.s b/gas/testsuite/gas/aarch64/sve-movprfx_28.s
new file mode 100644 (file)
index 0000000..9ef0ad5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_28.s
@@ -0,0 +1,45 @@
+       .text
+       .arch armv8-a+sve+bf16
+
+f:
+       // OK
+       movprfx z0.s, p1/m, z1.s
+       bfcvt z0.h, p1/m, z2.s
+
+       // OK
+       movprfx z0.s, p1/z, z1.s
+       bfcvt z0.h, p1/m, z2.s
+
+       // Wrong size
+       movprfx z0.h, p1/m, z1.h
+       bfcvt z0.h, p1/m, z2.s
+
+       // Wrong size
+       movprfx z0.h, p1/z, z1.h
+       bfcvt z0.h, p1/m, z2.s
+
+       // OK
+       movprfx z0, z1
+       bfcvt z0.h, p1/m, z2.s
+
+       // Not prefixable
+       movprfx z0, z1
+       bfcvtnt z0.h, p1/m, z2.s
+
+       // Not prefixable
+       movprfx z0.s, p1/m, z1.s
+       bfcvtnt z0.h, p1/m, z2.s
+
+       // Not prefixable
+       movprfx z0.s, p1/z, z1.s
+       bfcvtnt z0.h, p1/m, z2.s
+
+       // Not prefixable
+       movprfx z0.h, p1/m, z1.h
+       bfcvtnt z0.h, p1/m, z2.s
+
+       // Not prefixable
+       movprfx z0.h, p1/z, z1.h
+       bfcvtnt z0.h, p1/m, z2.s
+
+       ret
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 975d7e6bfb4020fb4076102c5a5754471d339e61..dd41d8850032f4c571f836af7775bfe7ca44999f 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
+       Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
+
 2020-01-30  Alan Modra  <amodra@gmail.com>
 
        * m32c-ibld.c: Regenerate.
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 2a9941267312bc5541cfc144f8a866856fd358c4..2bc69a38ee0ddad72a4a97cd40c1d4235a6621d1 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5107,8 +5107,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
   BFLOAT16_SVE_INSNC ("bfdot",  0x64608000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
   BFLOAT16_SVE_INSNC ("bfdot",  0x64604000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
   BFLOAT16_SVE_INSNC ("bfmmla",  0x6460e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-  BFLOAT16_SVE_INSNC ("bfcvt",  0x658aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0),
-  BFLOAT16_SVE_INSNC ("bfcvtnt",  0x648aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0),
+  BFLOAT16_SVE_INSNC ("bfcvt",  0x658aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  BFLOAT16_SVE_INSNC ("bfcvtnt",  0x648aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0, 0),
   BFLOAT16_SVE_INSNC ("bfmlalt",  0x64e08400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
   BFLOAT16_SVE_INSNC ("bfmlalb",  0x64e08000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
   BFLOAT16_SVE_INSNC ("bfmlalt",  0x64e04400, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
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