clk: tegra: pllp_out2 divider is int only

The pllp_out2 should be integer only, the fractional bit should always be 0.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 797e58f2f81162a27d2b6bbd79af36bf6c4df09e..2dd9b0094c9718989b4eef9099caf2b2b4d177c8 100644 (file)
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1200,8 +1200,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
        /* PLLP_OUT2 */
        clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
                                clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
-                               TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
-                               &pll_div_lock);
+                               TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
+                               8, 1, &pll_div_lock);
        clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
                                clk_base + PLLP_OUTA, 17, 16,
                                CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,