amd\powerplay Implement get dal power level

Implement get dal power level and simple clock info

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 215757e0ad763a8ea39752f14b2f86815fd55f92..0b9876daa8dcba6a8ece0b6bc2a0df6a3966078b 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -619,3 +619,16 @@ int amd_powerplay_display_configuration_change(void *handle, const void *input)
        phm_store_dal_configuration_data(hwmgr, display_config);
        return 0;
 }
+
+int amd_powerplay_get_display_power_level(void *handle,  void *output)
+{
+       struct pp_hwmgr  *hwmgr;
+
+       if (handle == NULL || output == NULL)
+               return -EINVAL;
+
+       hwmgr = ((struct pp_instance *)handle)->hwmgr;
+
+       return phm_get_dal_power_level(hwmgr,
+                       (struct pp_dal_clock_info *)output);
+}

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 13b5bef384f6a80eb12f0900ae87bd30e18aefdc..a745acf9c1816a19938af1165cd5217eabd8fe5a 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1544,7 +1544,7 @@ static void cz_hw_print_display_cfg(
                        display_cfg->cpu_pstate_separation_time);
 }
 
-int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
+ static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 {
        struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
        uint32_t data = 0;
@@ -1576,7 +1576,7 @@ int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
        return 0;
 }
 
-int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
+ static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
                        bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
 {
        struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
@@ -1596,6 +1596,28 @@ int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
        return 0;
 }
 
+ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
+               struct pp_dal_clock_info*info)
+{
+       uint32_t i;
+       const struct phm_clock_voltage_dependency_table * table =
+                       hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
+       const struct phm_clock_and_voltage_limits* limits =
+                       &hwmgr->dyn_state.max_clock_voltage_on_ac;
+
+       info->engine_max_clock = limits->sclk;
+       info->memory_max_clock = limits->mclk;
+
+       for (i = table->count - 1; i > 0; i--) {
+
+               if (limits->vddc >= table->entries[i].v) {
+                       info->level = table->entries[i].clk;
+                       return 0;
+               }
+       }
+       return -EINVAL;
+}
+
 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
        .backend_init = cz_hwmgr_backend_init,
        .backend_fini = cz_hwmgr_backend_fini,
@@ -1614,6 +1636,7 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = {
        .print_current_perforce_level = cz_print_current_perforce_level,
        .set_cpu_power_state = cz_set_cpu_power_state,
        .store_cc6_data = cz_store_cc6_data,
+       .get_dal_power_level= cz_get_dal_power_level,
 };
 
 int cz_hwmgr_init(struct pp_hwmgr *hwmgr)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 31b0dc3b10a22131df36319098878d7d0d6e0343..d24a41964fbe507f646b35d83962481452de9bea 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -261,6 +261,15 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
 
 }
 
+int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
+               struct pp_dal_clock_info*info)
+{
+       if (hwmgr == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
+               return -EINVAL;
+
+       return hwmgr->hwmgr_func->get_dal_power_level(hwmgr,info);
+}
+
 int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 {
        if (hwmgr != NULL && hwmgr->hwmgr_func->set_cpu_power_state != NULL)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index efa23c182bd0b3ac66cb64d1a2d7fcaacfadb2e1..2ec8c22d43480d5cfe7a0286faa3e63e52dbc588 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -138,6 +138,12 @@ struct amd_pp_display_configuration {
        uint32_t cpu_pstate_separation_time;
 };
 
+struct amd_pp_dal_clock_info {
+       uint32_t        engine_max_clock;
+       uint32_t        memory_max_clock;
+       uint32_t        level;
+};
+
 enum {
        PP_GROUP_UNKNOWN = 0,
        PP_GROUP_GFX = 1,
@@ -212,4 +218,7 @@ int amd_powerplay_fini(void *handle);
 
 int amd_powerplay_display_configuration_change(void *handle, const void *input);
 
+int amd_powerplay_get_display_power_level(void *handle,  void *output);
+
+
 #endif /* _AMD_POWERPLAY_H_ */

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index 820622dfe7531cb49fb42a374583774d65ecfe9f..a3b93cd3f739cd7107e805c3f284a2dea96323bf 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -323,6 +323,29 @@ struct phm_clocks {
        uint32_t clock[MAX_NUM_CLOCKS];
 };
 
+enum PP_DAL_POWERLEVEL {
+       PP_DAL_POWERLEVEL_INVALID = 0,
+       PP_DAL_POWERLEVEL_ULTRALOW,
+       PP_DAL_POWERLEVEL_LOW,
+       PP_DAL_POWERLEVEL_NOMINAL,
+       PP_DAL_POWERLEVEL_PERFORMANCE,
+
+       PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
+       PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
+       PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
+       PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
+       PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
+       PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
+       PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
+       PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
+};
+
+struct pp_dal_clock_info {
+       uint32_t                engine_max_clock;/*dal validation clock on AC*/
+       uint32_t                memory_max_clock;/*dal validation clock on AC*/
+       enum PP_DAL_POWERLEVEL  level;  /*number of levels for the given clocks*/
+};
+
 extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
 extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
 extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
@@ -354,7 +377,10 @@ extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
                                 bool *equal);
 
 extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
-                   const struct amd_pp_display_configuration *display_config);
+               const struct amd_pp_display_configuration *display_config);
+
+extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
+               struct pp_dal_clock_info*info);
 
 extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
 

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index ec871ebc12eb65e9f9e0c68c43acc7d7a44905b2..c9fcc0c32f94aad71c542be16fba7fcc3b0c021a 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -85,22 +85,6 @@ enum PHM_BackEnd_Magic {
        PHM_Cz_Magic          = 0x67DCBA25
 };
 
-enum PP_DAL_POWERLEVEL {
-       PP_DAL_POWERLEVEL_INVALID = 0,
-       PP_DAL_POWERLEVEL_ULTRALOW,
-       PP_DAL_POWERLEVEL_LOW,
-       PP_DAL_POWERLEVEL_NOMINAL,
-       PP_DAL_POWERLEVEL_PERFORMANCE,
-
-       PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
-       PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
-       PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
-       PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
-       PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
-       PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
-       PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
-       PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
-};
 
 #define PHM_PCIE_POWERGATING_TARGET_GFX            0
 #define PHM_PCIE_POWERGATING_TARGET_DDI            1
@@ -340,6 +324,8 @@ struct pp_hwmgr_func {
        int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
                                bool cc6_disable, bool pstate_disable,
                                bool pstate_switch_disable);
+       int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
+                       struct pp_dal_clock_info*info);
 };
 
 struct pp_table_func {