clk: tegra: Correct bit width for PMC output clock mux

The bit field for setting the clock mux for the PMC output clocks is a
2-bit field and has always been a 2-bit field for all Tegra devices that
have these clocks (starting with Tegra30). However, the PMC clock driver
incorrectly specifies that this bit field is 3 bits wide and this causes
other bits in the register to be over-written when setting up the mux.
Therefore, correct the width for PMC clock mux to prevent over-writing
other fields.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
index 91377abfefa19189f82ba32e12a6e0484ed8f9c9..36469a2ca3852fe2b297ed92a0280a3d14eff63d 100644 (file)
--- a/drivers/clk/tegra/clk-tegra-pmc.c
+++ b/drivers/clk/tegra/clk-tegra-pmc.c
@@ -97,7 +97,7 @@ void __init tegra_pmc_clk_init(void __iomem *pmc_base,
                clk = clk_register_mux(NULL, data->mux_name, data->parents,
                                data->num_parents, CLK_SET_RATE_NO_REPARENT,
                                pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
-                               3, 0, &clk_out_lock);
+                               2, 0, &clk_out_lock);
                *dt_clk = clk;