tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110
tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100
tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
-tune-$(CONFIG_CPU_V6) :=-mtune=strongarm
+tune-$(CONFIG_CPU_V6) :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
# Need -Uarm for gcc < 3.x
CFLAGS_ABI :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,)
#define EXPORT_SYMBOL_ALIAS(sym,orig) \
EXPORT_CRC_ALIAS(sym) \
- const struct kernel_symbol __ksymtab_##sym \
- __attribute__((section("__ksymtab"))) = \
+ static const struct kernel_symbol __ksymtab_##sym \
+ __attribute_used__ __attribute__((section("__ksymtab"))) = \
{ (unsigned long)&orig, #sym };
/*
.endm
.Larm700bug:
- ldr r0, [sp, #S_PSR] @ Get calling cpsr
- sub lr, lr, #4
- str lr, [r8]
- msr spsr_cxsf, r0
ldmia sp, {r0 - lr}^ @ Get calling r0 - lr
mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
- movs pc, lr
+ subs pc, lr, #4
#else
.macro arm710_bug_check, instr, temp
.endm
static int chip0_map[] = { 0 };
static int chip1_map[] = { 1 };
-struct mtd_partition anubis_default_nand_part[] = {
+static struct mtd_partition anubis_default_nand_part[] = {
[0] = {
.name = "Boot Agent",
.size = SZ_16K,
static int chip1_map[] = { 2 };
static int chip2_map[] = { 3 };
-struct mtd_partition bast_default_nand_part[] = {
+static struct mtd_partition bast_default_nand_part[] = {
[0] = {
.name = "Boot Agent",
.size = SZ_16K,
* better IO routines can be written and tested
*/
-struct dm9000_plat_data bast_dm9k_platdata = {
+static struct dm9000_plat_data bast_dm9k_platdata = {
.flags = DM9000_PLATF_16BITONLY
};
* better IO routines can be written and tested
*/
-struct dm9000_plat_data vr1000_dm9k_platdata = {
+static struct dm9000_plat_data vr1000_dm9k_platdata = {
.flags = DM9000_PLATF_16BITONLY,
};
&s3c_uart2
};
-/* store our uart devices for the serial driver console */
-struct platform_device *s3c2410_uart_devices[3];
-
static int s3c2410_uart_count = 0;
/* uart registration process */
#ifdef CONFIG_PM
-struct sleep_save s3c2440_sleep[] = {
+static struct sleep_save s3c2440_sleep[] = {
SAVE_ITEM(S3C2440_DSC0),
SAVE_ITEM(S3C2440_DSC1),
SAVE_ITEM(S3C2440_GPJDAT),
* as a driver which may support both 2410 and 2440 may try and use it.
*/
-int __init s3c2440_core_init(void)
+static int __init s3c2440_core_init(void)
{
return sysdev_class_register(&s3c2440_sysclass);
}
#include <asm/hardware/clock.h>
#include "clock.h"
+#include "cpu.h"
static unsigned long timer_startval;
static unsigned long timer_usec_ticks;
}
static int proc_alignment_write(struct file *file, const char __user *buffer,
- unsigned long count, void *data)
+ unsigned long count, void *data)
{
char mode;
if (get_user(mode, buffer))
return -EFAULT;
if (mode >= '0' && mode <= '5')
- ai_usermode = mode - '0';
+ ai_usermode = mode - '0';
}
return count;
}
goto fault; \
} while (0)
-#define put32_unaligned_check(val,addr) \
+#define put32_unaligned_check(val,addr) \
__put32_unaligned_check("strb", val, addr)
#define put32t_unaligned_check(val,addr) \
return TYPE_LDST;
user:
- if (LDST_L_BIT(instr)) {
- unsigned long val;
- get16t_unaligned_check(val, addr);
+ if (LDST_L_BIT(instr)) {
+ unsigned long val;
+ get16t_unaligned_check(val, addr);
- /* signed half-word? */
- if (instr & 0x40)
- val = (signed long)((signed short) val);
+ /* signed half-word? */
+ if (instr & 0x40)
+ val = (signed long)((signed short) val);
- regs->uregs[rd] = val;
- } else
- put16t_unaligned_check(regs->uregs[rd], addr);
+ regs->uregs[rd] = val;
+ } else
+ put16t_unaligned_check(regs->uregs[rd], addr);
- return TYPE_LDST;
+ return TYPE_LDST;
fault:
return TYPE_FAULT;
unsigned long val;
get32_unaligned_check(val, addr);
regs->uregs[rd] = val;
- get32_unaligned_check(val, addr+4);
- regs->uregs[rd+1] = val;
+ get32_unaligned_check(val, addr + 4);
+ regs->uregs[rd + 1] = val;
} else {
put32_unaligned_check(regs->uregs[rd], addr);
- put32_unaligned_check(regs->uregs[rd+1], addr+4);
+ put32_unaligned_check(regs->uregs[rd + 1], addr + 4);
}
return TYPE_LDST;
unsigned long val;
get32t_unaligned_check(val, addr);
regs->uregs[rd] = val;
- get32t_unaligned_check(val, addr+4);
- regs->uregs[rd+1] = val;
+ get32t_unaligned_check(val, addr + 4);
+ regs->uregs[rd + 1] = val;
} else {
put32t_unaligned_check(regs->uregs[rd], addr);
- put32t_unaligned_check(regs->uregs[rd+1], addr+4);
+ put32t_unaligned_check(regs->uregs[rd + 1], addr + 4);
}
return TYPE_LDST;
if (LDST_P_EQ_U(instr)) /* U = P */
eaddr += 4;
- /*
+ /*
* For alignment faults on the ARM922T/ARM920T the MMU makes
* the FSR (and hence addr) equal to the updated base address
* of the multiple access rather than the restored value.
/* 6.5.1 Format 3: */
case 0x4800 >> 11: /* 7.1.28 LDR(3) */
/* NOTE: This case is not technically possible. We're
- * loading 32-bit memory data via PC relative
+ * loading 32-bit memory data via PC relative
* addressing mode. So we can and should eliminate
* this case. But I'll leave it here for now.
*/
if (fault) {
type = TYPE_FAULT;
- goto bad_or_fault;
+ goto bad_or_fault;
}
if (user_mode(regs))
#include <linux/string.h>
#include <asm/system.h>
-/* forward declarations */
-unsigned int EmulateCPDO(const unsigned int);
-unsigned int EmulateCPDT(const unsigned int);
-unsigned int EmulateCPRT(const unsigned int);
-
/* Reset the FPA11 chip. Called to initialize and reset the emulator. */
static void resetFPA11(void)
{
extern int8 SetRoundingPrecision(const unsigned int);
extern void nwfpe_init_fpa(union fp_state *fp);
+extern unsigned int EmulateAll(unsigned int opcode);
+
+extern unsigned int EmulateCPDT(const unsigned int opcode);
+extern unsigned int EmulateCPDO(const unsigned int opcode);
+extern unsigned int EmulateCPRT(const unsigned int opcode);
+
+/* fpa11_cpdt.c */
+extern unsigned int PerformLDF(const unsigned int opcode);
+extern unsigned int PerformSTF(const unsigned int opcode);
+extern unsigned int PerformLFM(const unsigned int opcode);
+extern unsigned int PerformSFM(const unsigned int opcode);
+
+/* single_cpdo.c */
+
+extern unsigned int SingleCPDO(struct roundingData *roundData,
+ const unsigned int opcode, FPREG * rFd);
+/* double_cpdo.c */
+extern unsigned int DoubleCPDO(struct roundingData *roundData,
+ const unsigned int opcode, FPREG * rFd);
+
#endif
#include "fpa11.inl"
#include "fpmodule.h"
#include "fpmodule.inl"
+#include "softfloat.h"
#ifdef CONFIG_FPE_NWFPE_XP
extern flag floatx80_is_nan(floatx80);
#endif
-extern flag float64_is_nan(float64);
-extern flag float32_is_nan(float32);
unsigned int PerformFLT(const unsigned int opcode);
unsigned int PerformFIX(const unsigned int opcode);
return (nRc);
}
+extern unsigned int checkCondition(const unsigned int opcode,
+ const unsigned int ccodes);
+
+extern const float64 float64Constant[];
+extern const float32 float32Constant[];
+
#endif
return (a != b) && (aSign ^ (a < b));
}
+extern flag float32_is_nan( float32 a );
+extern flag float64_is_nan( float64 a );
+
#endif
struct uart_port port;
struct timer_list timer;
unsigned int old_status;
- int txirq,rxirq;
+ int txirq,rxirq,rtsirq;
};
/*
imx_transmit_buffer(sport);
}
+static irqreturn_t imx_rtsint(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct imx_port *sport = (struct imx_port *)dev_id;
+ unsigned int val = USR1((u32)sport->port.membase)&USR1_RTSS;
+ unsigned long flags;
+
+ spin_lock_irqsave(&sport->port.lock, flags);
+
+ USR1((u32)sport->port.membase) = USR1_RTSD;
+ uart_handle_cts_change(&sport->port, !!val);
+ wake_up_interruptible(&sport->port.info->delta_msr_wait);
+
+ spin_unlock_irqrestore(&sport->port.lock, flags);
+ return IRQ_HANDLED;
+}
+
static irqreturn_t imx_txint(int irq, void *dev_id, struct pt_regs *regs)
{
struct imx_port *sport = (struct imx_port *)dev_id;
if (retval) goto error_out1;
retval = request_irq(sport->txirq, imx_txint, 0,
- "imx-uart", sport);
+ DRIVER_NAME, sport);
if (retval) goto error_out2;
+ retval = request_irq(sport->rtsirq, imx_rtsint, 0,
+ DRIVER_NAME, sport);
+ if (retval) goto error_out3;
+ set_irq_type(sport->rtsirq, IRQT_BOTHEDGE);
+
/*
* Finally, clear and enable interrupts
*/
+ USR1((u32)sport->port.membase) = USR1_RTSD;
UCR1((u32)sport->port.membase) |=
- (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_UARTEN);
+ (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
UCR2((u32)sport->port.membase) |= (UCR2_RXEN | UCR2_TXEN);
/*
return 0;
+error_out3:
+ free_irq(sport->txirq, sport);
error_out2:
free_irq(sport->rxirq, sport);
error_out1:
/*
* Free the interrupts
*/
+ free_irq(sport->rtsirq, sport);
free_irq(sport->txirq, sport);
free_irq(sport->rxirq, sport);
*/
UCR1((u32)sport->port.membase) &=
- ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_UARTEN);
+ ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
}
static void
* disable interrupts and drain transmitter
*/
old_ucr1 = UCR1((u32)sport->port.membase);
- UCR1((u32)sport->port.membase) &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN);
+ UCR1((u32)sport->port.membase) &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
while ( !(USR2((u32)sport->port.membase) & USR2_TXDC))
barrier();
{
.txirq = UART1_MINT_TX,
.rxirq = UART1_MINT_RX,
+ .rtsirq = UART1_MINT_RTS,
.port = {
.type = PORT_IMX,
.iotype = SERIAL_IO_MEM,
}, {
.txirq = UART2_MINT_TX,
.rxirq = UART2_MINT_RX,
+ .rtsirq = UART2_MINT_RTS,
.port = {
.type = PORT_IMX,
.iotype = SERIAL_IO_MEM,
UCR1((u32)sport->port.membase) =
(old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN)
- & ~(UCR1_TXMPTYEN | UCR1_RRDYEN);
+ & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
UCR2((u32)sport->port.membase) = old_ucr2 | UCR2_TXEN;
/*
/*
* Update the per-port timeout.
*/
- uart_update_timeout(port, termios->c_cflag, quot);
+ uart_update_timeout(port, termios->c_cflag, baud);
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
if (termios->c_iflag & INPCK)
static int probe_index = 0;
-int s3c24xx_serial_probe(struct device *_dev,
- struct s3c24xx_uart_info *info)
+static int s3c24xx_serial_probe(struct device *_dev,
+ struct s3c24xx_uart_info *info)
{
struct s3c24xx_uart_port *ourport;
struct platform_device *dev = to_platform_device(_dev);
return ret;
}
-int s3c24xx_serial_remove(struct device *_dev)
+static int s3c24xx_serial_remove(struct device *_dev)
{
struct uart_port *port = s3c24xx_dev_to_port(_dev);
#ifdef CONFIG_PM
-int s3c24xx_serial_suspend(struct device *dev, pm_message_t state, u32 level)
+static int s3c24xx_serial_suspend(struct device *dev, pm_message_t state,
+ u32 level)
{
struct uart_port *port = s3c24xx_dev_to_port(dev);
return 0;
}
-int s3c24xx_serial_resume(struct device *dev, u32 level)
+static int s3c24xx_serial_resume(struct device *dev, u32 level)
{
struct uart_port *port = s3c24xx_dev_to_port(dev);
struct s3c24xx_uart_port *ourport = to_ourport(port);
#define s3c24xx_serial_resume NULL
#endif
-int s3c24xx_serial_init(struct device_driver *drv,
- struct s3c24xx_uart_info *info)
+static int s3c24xx_serial_init(struct device_driver *drv,
+ struct s3c24xx_uart_info *info)
{
dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
return driver_register(drv);
#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
-#define DRCMR15 __REG(0x4000013c) /* Reserved */
-#define DRCMR16 __REG(0x40000140) /* Reserved */
+#define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */
+#define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */
#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
#define DRCMR39 __REG(0x4000019C) /* Reserved */
-
+#define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */
+#define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */
#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
+#ifdef CONFIG_CPU_S3C2440
+
+extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
+
+#endif /* CONFIG_CPU_S3C2440 */
+
+
#endif /* __ASSEMBLY__ */
#include <asm/sizes.h>