Merge tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux into...

Merge "changes for Broadcom SoCs":

- Dan fixes an error path in the BCM63xx SMP code

- Ray adds the relevant Kconfig selects to enable the Broadcom NAND driver on Cygnus

- Kevin provides a change to the Broadcom GISB arbiter driver to make it work with
  MIPS-based big-endian STB SoCs (this was a long-standing change that had dependencies on
  code in drivers/of/*)

- Gregory enables the use of GPIOLIB for brcmstb SoCs and bumps the number of GPIOs for
  these platforms

* tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux:
  ARM: brcmstb: Add default gpio number
  ARM: brcmstb: Select ARCH_WANT_OPTIONAL_GPIOLIB
  bus: brcmstb_gisb: Honor the "big-endian" and "native-endian" DT properties
  ARM: BCM: Enable NAND support for iProc SoCs
  ARM: BCM63xx: fix an error path in bcm63xx_pmb_power_on_cpu()

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b7a7d1556d964234599766cd10c92cf10747caf4..0d4eb0ebcb9f2e6d0e90a413d5d82c6dcbd9cb3a 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1509,7 +1509,8 @@ config ARM_PSCI
 # selected platforms.
 config ARCH_NR_GPIO
        int
-       default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
+       default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
+               ARCH_ZYNQ
        default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
                SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
        default 416 if ARCH_SUNXI

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 8b11f44bb36e5a3dcfe59cf331e18730e71c9ec5..e9184feffc4e5b55d46008be3f3587d2756ea6e3 100644 (file)
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -19,6 +19,7 @@ config ARCH_BCM_IPROC
        select ARCH_REQUIRE_GPIOLIB
        select ARM_AMBA
        select PINCTRL
+       select MTD_NAND_BRCMNAND
        help
          This enables support for systems based on Broadcom IPROC architected SoCs.
          The IPROC complex contains one or more ARM CPUs along with common
@@ -144,6 +145,7 @@ config ARCH_BRCMSTB
        select BRCMSTB_GISB_ARB
        select BRCMSTB_L2_IRQ
        select BCM7120_L2_IRQ
+       select ARCH_WANT_OPTIONAL_GPIOLIB
        help
          Say Y if you intend to run the kernel on a Broadcom ARM-based STB
          chipset.

diff --git a/arch/arm/mach-bcm/bcm63xx_pmb.c b/arch/arm/mach-bcm/bcm63xx_pmb.c
index c39752b85b92ad2cb6f96a5ba1513c8b8f243fd3..de061ec5a47964c99cba838bac515fba48b475eb 100644 (file)
--- a/arch/arm/mach-bcm/bcm63xx_pmb.c
+++ b/arch/arm/mach-bcm/bcm63xx_pmb.c
@@ -150,7 +150,7 @@ int bcm63xx_pmb_power_on_cpu(struct device_node *dn)
         */
        ret = bpcm_rd(base, addr, ARM_CONTROL, &ctrl);
        if (ret)
-               return ret;
+               goto out;
 
        if (ctrl & CPU_RESET_N(cpu)) {
                pr_info("PMB: CPU%d is already powered on\n", cpu);

diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c
index 738612c45266c1b11f1319ae95275dcc881b8590..f364fa4d24ebffa8b9021036b3e3f22d0018da40 100644 (file)
--- a/drivers/bus/brcmstb_gisb.c
+++ b/drivers/bus/brcmstb_gisb.c
@@ -91,6 +91,7 @@ static const int gisb_offsets_bcm7445[] = {
 struct brcmstb_gisb_arb_device {
        void __iomem    *base;
        const int       *gisb_offsets;
+       bool            big_endian;
        struct mutex    lock;
        struct list_head next;
        u32 valid_mask;
@@ -108,7 +109,10 @@ static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
        if (offset == -1)
                return 1;
 
-       return ioread32(gdev->base + offset);
+       if (gdev->big_endian)
+               return ioread32be(gdev->base + offset);
+       else
+               return ioread32(gdev->base + offset);
 }
 
 static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
@@ -117,7 +121,11 @@ static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
 
        if (offset == -1)
                return;
-       iowrite32(val, gdev->base + reg);
+
+       if (gdev->big_endian)
+               iowrite32be(val, gdev->base + reg);
+       else
+               iowrite32(val, gdev->base + reg);
 }
 
 static ssize_t gisb_arb_get_timeout(struct device *dev,
@@ -296,6 +304,7 @@ static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
                return -EINVAL;
        }
        gdev->gisb_offsets = of_id->data;
+       gdev->big_endian = of_device_is_big_endian(dn);
 
        err = devm_request_irq(&pdev->dev, timeout_irq,
                                brcmstb_gisb_timeout_handler, 0, pdev->name,