drm/i915: add GEN5_IRQ_FINI

Same as the _INIT macro: the goal is to reuse the GEN8 macros, but
there are still some slight differences.

v2: - Rebase.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bc7e2303cd4fec7a41713c6dc48da77161a74a1b..26bfe1bfe06e3869d2040a312fa88be20417c092 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -101,6 +101,12 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
        POSTING_READ(type##IIR); \
 } while (0)
 
+#define GEN5_IRQ_FINI(type) do { \
+       I915_WRITE(type##IMR, 0xffffffff); \
+       I915_WRITE(type##IER, 0); \
+       I915_WRITE(type##IIR, I915_READ(type##IIR)); \
+} while (0)
+
 /* For display hotplug interrupt */
 static void
 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
@@ -3353,22 +3359,16 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
 
        I915_WRITE(HWSTAM, 0xffffffff);
 
-       I915_WRITE(DEIMR, 0xffffffff);
-       I915_WRITE(DEIER, 0x0);
-       I915_WRITE(DEIIR, I915_READ(DEIIR));
+       GEN5_IRQ_FINI(DE);
        if (IS_GEN7(dev))
                I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
 
-       I915_WRITE(GTIMR, 0xffffffff);
-       I915_WRITE(GTIER, 0x0);
-       I915_WRITE(GTIIR, I915_READ(GTIIR));
+       GEN5_IRQ_FINI(GT);
 
        if (HAS_PCH_NOP(dev))
                return;
 
-       I915_WRITE(SDEIMR, 0xffffffff);
-       I915_WRITE(SDEIER, 0x0);
-       I915_WRITE(SDEIIR, I915_READ(SDEIIR));
+       GEN5_IRQ_FINI(SDE);
        if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
                I915_WRITE(SERR_INT, I915_READ(SERR_INT));
 }