int regno;
for (regno = 0; regno < FP0_REGNUM; regno++)
- regcache_collect (regno, vals + regno);
+ if (register_cached (regno))
+ regcache_collect (regno, vals + regno);
}
static void
int regno;
for (regno = 0; regno < FP0_REGNUM; regno++)
- regcache_collect (regno, vals + regno);
+ if (register_cached (regno))
+ regcache_collect (regno, vals + regno);
}
/* Store the floating point registers into a double array. */
int regno;
for (regno = FP0_REGNUM; regno < FPLAST_REGNUM; regno++)
- regcache_collect (regno, vals + regno);
+ if (register_cached (regno))
+ regcache_collect (regno, vals + regno);
}
/* Store the special registers into the specified 64-bit and 32-bit
gdb_assert (sizeof (*iar) == REGISTER_RAW_SIZE (regno));
- regcache_collect (regno, iar);
- regcache_collect (regno + 1, msr);
- regcache_collect (regno + 2, cr);
- regcache_collect (regno + 3, lr);
- regcache_collect (regno + 4, ctr);
- regcache_collect (regno + 5, xer);
+ if (register_cached (regno))
+ regcache_collect (regno, iar);
+ if (register_cached (regno + 1))
+ regcache_collect (regno + 1, msr);
+ if (register_cached (regno + 2))
+ regcache_collect (regno + 2, cr);
+ if (register_cached (regno + 3))
+ regcache_collect (regno + 3, lr);
+ if (register_cached (regno + 4))
+ regcache_collect (regno + 4, ctr);
+ if (register_cached (regno + 5))
+ regcache_collect (regno + 5, xer);
}
static void
sizeof (long) == 4). */
gdb_assert (sizeof (*iar) == REGISTER_RAW_SIZE (regno));
- regcache_collect (regno, iar);
- regcache_collect (regno + 1, msr);
- regcache_collect (regno + 2, cr);
- regcache_collect (regno + 3, lr);
- regcache_collect (regno + 4, ctr);
- regcache_collect (regno + 5, xer);
+ if (register_cached (regno))
+ regcache_collect (regno, iar);
+ if (register_cached (regno + 1))
+ regcache_collect (regno + 1, msr);
+ if (register_cached (regno + 2))
+ regcache_collect (regno + 2, cr);
+ if (register_cached (regno + 3))
+ regcache_collect (regno + 3, lr);
+ if (register_cached (regno + 4))
+ regcache_collect (regno + 4, ctr);
+ if (register_cached (regno + 5))
+ regcache_collect (regno + 5, xer);
}
/* Store all registers into pthread PDTID, which doesn't have a kernel
/* Collect general-purpose register values from the regcache. */
for (i = 0; i < 32; i++)
- {
- if (arch64)
- {
- regcache_collect (i, (void *) &int64);
- ctx.gpr[i] = int64;
- }
- else
- {
- regcache_collect (i, (void *) &int32);
- ctx.gpr[i] = int32;
- }
- }
+ if (register_cached (i))
+ {
+ if (arch64)
+ {
+ regcache_collect (i, (void *) &int64);
+ ctx.gpr[i] = int64;
+ }
+ else
+ {
+ regcache_collect (i, (void *) &int32);
+ ctx.gpr[i] = int32;
+ }
+ }
/* Collect floating-point register values from the regcache. */
fill_fprs (ctx.fpr);
unsigned long tmp_iar, tmp_msr, tmp_cr, tmp_lr, tmp_ctr, tmp_xer;
fill_sprs32 (&tmp_iar, &tmp_msr, &tmp_cr, &tmp_lr, &tmp_ctr, &tmp_xer);
- ctx.iar = tmp_iar;
- ctx.msr = tmp_msr;
- ctx.cr = tmp_cr;
- ctx.lr = tmp_lr;
- ctx.ctr = tmp_ctr;
- ctx.xer = tmp_xer;
+ if (register_cached (FIRST_UISA_SP_REGNUM))
+ ctx.iar = tmp_iar;
+ if (register_cached (FIRST_UISA_SP_REGNUM + 1))
+ ctx.msr = tmp_msr;
+ if (register_cached (FIRST_UISA_SP_REGNUM + 2))
+ ctx.cr = tmp_cr;
+ if (register_cached (FIRST_UISA_SP_REGNUM + 3))
+ ctx.lr = tmp_lr;
+ if (register_cached (FIRST_UISA_SP_REGNUM + 4))
+ ctx.ctr = tmp_ctr;
+ if (register_cached (FIRST_UISA_SP_REGNUM + 5))
+ ctx.xer = tmp_xer;
}
status = pthdb_pthread_setcontext (pd_session, pdtid, &ctx);
{
if (arch64)
{
+ /* Pre-fetch: some regs may not be in the cache. */
+ ptrace64aix (PTT_READ_GPRS, tid, (unsigned long) gprs64, 0, NULL);
fill_gprs64 (gprs64);
ptrace64aix (PTT_WRITE_GPRS, tid, (unsigned long) gprs64, 0, NULL);
}
else
{
+ /* Pre-fetch: some regs may not be in the cache. */
+ ptrace32 (PTT_READ_GPRS, tid, gprs32, 0, NULL);
fill_gprs32 (gprs32);
ptrace32 (PTT_WRITE_GPRS, tid, gprs32, 0, NULL);
}
if (regno == -1 || (regno >= FP0_REGNUM && regno <= FPLAST_REGNUM))
{
+ /* Pre-fetch: some regs may not be in the cache. */
+ ptrace32 (PTT_READ_FPRS, tid, (int *) fprs, 0, NULL);
fill_fprs (fprs);
ptrace32 (PTT_WRITE_FPRS, tid, (int *) fprs, 0, NULL);
}
{
if (arch64)
{
- /* Must read first, not all of it's in the cache. */
+ /* Pre-fetch: some registers won't be in the cache. */
ptrace64aix (PTT_READ_SPRS, tid,
(unsigned long) &sprs64, 0, NULL);
fill_sprs64 (&sprs64.pt_iar, &sprs64.pt_msr, &sprs64.pt_cr,
}
else
{
- /* Must read first, not all of it's in the cache. */
+ /* Pre-fetch: some registers won't be in the cache. */
ptrace32 (PTT_READ_SPRS, tid, (int *) &sprs32, 0, NULL);
fill_sprs32 (&sprs32.pt_iar, &sprs32.pt_msr, &sprs32.pt_cr,
&sprs32.pt_lr, &sprs32.pt_ctr, &sprs32.pt_xer);
if (REGISTER_RAW_SIZE (LAST_UISA_SP_REGNUM))
- regcache_collect (LAST_UISA_SP_REGNUM, &sprs32.pt_mq);
+ if (register_cached (LAST_UISA_SP_REGNUM))
+ regcache_collect (LAST_UISA_SP_REGNUM, &sprs32.pt_mq);
ptrace32 (PTT_WRITE_SPRS, tid, (int *) &sprs32, 0, NULL);
}
}
}
-/* Prepare to copy the register cache to the child:
- The register cache must be fully fetched and up to date. */
-
-static void
-ops_prepare_to_store (void)
-{
- int regno;
-
- if (!PD_TID (inferior_ptid))
- base_ops.to_prepare_to_store ();
- else
- for (regno = 0; regno < NUM_REGS; regno++)
- if (!register_cached (regno))
- target_fetch_registers (regno);
-}
-
/* Transfer LEN bytes of memory from GDB address MYADDR to target
address MEMADDR if WRITE and vice versa otherwise. */
ops.to_wait = ops_wait;
ops.to_fetch_registers = ops_fetch_registers;
ops.to_store_registers = ops_store_registers;
- ops.to_prepare_to_store = ops_prepare_to_store;
ops.to_xfer_memory = ops_xfer_memory;
/* No need for ops.to_create_inferior, because we activate thread
debugging when the inferior reaches pd_brk_addr. */