ARM: shmobile: lager: Fix QSPI mode of SPI-Flash into mode3

In order to change into mode3, CPOL and CPHA bit of SPCMD register
of QSPI is changed. Mode3 can avoid intermediate voltage.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
[horms: Updated changelog and re-ordered properties]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 636d53bb87a27062b79afae3f009629e52fd63d3..bc257e8b1bf29d2ee836166782614a5b0d59786d 100644 (file)
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -397,6 +397,8 @@
                spi-max-frequency = <30000000>;
                spi-tx-bus-width = <4>;
                spi-rx-bus-width = <4>;
+               spi-cpha;
+               spi-cpol;
                m25p,fast-read;
 
                partition@0 {