* gencode.c (process_instructions): Correct handling of nor

	instruction.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 9acd9c3b3adff7e02f4a5abd95e2449687b8210d..3c0099f6d9f0c92d9095e1378f55d2b472369de3 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+       * gencode.c (process_instructions): Correct handling of nor
+       instruction.
+
 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
        * interp.c (sim_monitor): Improved monitor printf

diff --git a/sim/mips/gencode.c b/sim/mips/gencode.c
index 1e0dbf7a12cc200331988d697b7e88557b4aedbb..0dda11cd014e161b0b4e8313917296748cf2ecfb 100644 (file)
--- a/sim/mips/gencode.c
+++ b/sim/mips/gencode.c
@@ -1240,7 +1240,7 @@ process_instructions(doarch,features)
        break ;
 
        case OR:
-        printf("   GPR[destreg] = (%sop1 | op2);\n",((MIPS_DECODE[loop].flags & NOT) ? "~" : ""));
+        printf("   GPR[destreg] = %s(op1 | op2);\n",((MIPS_DECODE[loop].flags & NOT) ? "~" : ""));
        break ;
 
        case XOR: