clk: rockchip: add clock node in PD_VIDEO

This patch add the clock node in PD_VIDEO

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 3dfc5e3a074cc145d3235961da081c1223e346a2..35c3297d05bac6f7103e0ed6986f0daba9022e78 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -296,6 +296,20 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
        COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
                        RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
                        RK3288_CLKGATE_CON(3), 11, GFLAGS),
+       /*
+        * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
+        * so we ignore the mux and make clocks nodes as following,
+        */
+       GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
+               RK3288_CLKGATE_CON(9), 0, GFLAGS),
+       /*
+        * We introduce a virtul node of hclk_vodec_pre_v to split one clock
+        * struct with a gate and a fix divider into two node in software.
+        */
+       GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0,
+               RK3288_CLKGATE_CON(3), 10, GFLAGS),
+       GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
+               RK3288_CLKGATE_CON(9), 1, GFLAGS),
 
        COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
                        RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
@@ -705,6 +719,12 @@ static void __init rk3288_clk_init(struct device_node *np)
                pr_warn("%s: could not register clock usb480m: %ld\n",
                        __func__, PTR_ERR(clk));
 
+       clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
+                                       "hclk_vcodec_pre_v", 0, 1, 4);
+       if (IS_ERR(clk))
+               pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
+                       __func__, PTR_ERR(clk));
+
        rockchip_clk_register_plls(rk3288_pll_clks,
                                   ARRAY_SIZE(rk3288_pll_clks),
                                   RK3288_GRF_SOC_STATUS);