ARM: mvebu: add Device Tree description of AHCI interfaces on Armada 38x
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tue, 15 Apr 2014 15:00:04 +0000 (17:00 +0200)
committerJason Cooper <jason@lakedaemon.net>
Sat, 26 Apr 2014 00:26:36 +0000 (00:26 +0000)
The Marvell Armada 38x processors contain two AHCI compatible
interfaces. This commit adds the Device Tree description of those
interfaces at the SoC level, and also enables them on the Armada 385
DB platform, which allows access to both interfaces through SATA
ports.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397574006-5868-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
arch/arm/boot/dts/armada-385-db.dts
arch/arm/boot/dts/armada-38x.dtsi

index 959aeedc22d3b95ffb5c02280f63eff8da916667..1ad988b3a75c2ee5ef585ba455066af33989bd38 100644 (file)
                                };
                        };
 
+                       sata@a8000 {
+                               status = "okay";
+                       };
+
+                       sata@e0000 {
+                               status = "okay";
+                       };
+
                        flash@d0000 {
                                status = "okay";
                                num-cs = <1>;
index 7e1b2434b10c44dcfc6621feb58873a77a710863..7c3f3ddd9096f0214b53590b3ca14e556296fbcf 100644 (file)
                                reg = <0x72004 0x4>;
                        };
 
+                       sata@a8000 {
+                               compatible = "marvell,armada-380-ahci";
+                               reg = <0xa8000 0x2000>;
+                               interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&gateclk 15>;
+                               status = "disabled";
+                       };
+
+                       sata@e0000 {
+                               compatible = "marvell,armada-380-ahci";
+                               reg = <0xe0000 0x2000>;
+                               interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&gateclk 30>;
+                               status = "disabled";
+                       };
+
                        coredivclk: clock@e4250 {
                                compatible = "marvell,armada-380-corediv-clock";
                                reg = <0xe4250 0xc>;
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