opcodes/

	* microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
	update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
	and increase MAX_OPCODES.
	(op_code_struct):  add mbar and sleep
	* microblaze-opcm.h (microblaze_instr): add mbar
	Define IMM_MBAR and IMM5_MBAR_MASK
	* microblaze-dis.c: Add get_field_imm5_mbar
	(print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE

gas/
	* config/tc-microblaze.c (md_assemble): Add support for INST_TYPE_IMM5

gas/testsuite/
	* gas/microblaze/allinsn.s: Add mbar and sleep
	* gas/microblaze/allinsn.d: Likewise

diff --git a/gas/ChangeLog b/gas/ChangeLog
index a3a33d8aa39fec8c48277521cb42a59ca6f85cd8..f1e62076839d0153d038d73c1dc7855bac7674be 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2012-11-14  David Holsgrove  <david.holsgrove@xilinx.com>
+
+       * config/tc-microblaze.c (md_assemble): Add support for INST_TYPE_IMM5
+
 2012-11-14  Ulrich Weigand  <uweigand@de.ibm.com>
 
        * config/tc-ppc.c (md_apply_fix): Leave field zero when emitting

diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
index 04dfa1ef987caa4927bbfed9a7b6914c82958ab5..b71383bd88bb2d7fdb862fdf1da54db6407cbfeb 100644 (file)
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -1605,6 +1605,24 @@ md_assemble (char * str)
       output = frag_more (isize);
       break;
 
+    case INST_TYPE_IMM5:
+      if (strcmp(op_end, ""))
+        op_end = parse_imm (op_end + 1, & exp, MIN_IMM5, MAX_IMM5);
+      else
+        as_fatal(_("Error in statement syntax"));
+      if (exp.X_op != O_constant) {
+        as_warn(_("Symbol used as immediate for mbar instruction"));
+      } else {
+        output = frag_more (isize);
+        immed = exp.X_add_number;
+      }
+      if (immed != (immed % 32)) {
+        as_warn(_("Immediate value for mbar > 32. using <value %% 32>"));
+        immed = immed % 32;
+      }
+      inst |= (immed << IMM_MBAR);
+      break;
+
     default:
       as_fatal (_("unimplemented opcode \"%s\""), name);
     }

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index c2a66c8f416179287cd9b48008fc3d96e9e48455..51405aaf0e64977034becc5790746fbfd7dc4173 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,4 +1,9 @@
-2012-11-08  David Holsgrove  <david.holsgrove@xilinx.com>
+2012-11-14  David Holsgrove  <david.holsgrove@xilinx.com>
+
+       * gas/microblaze/allinsn.s: Add mbar and sleep
+       * gas/microblaze/allinsn.d: Likewise
+
+2012-11-14  David Holsgrove  <david.holsgrove@xilinx.com>
 
        * gas/microblaze/allinsn.s: Add clz insn
        * gas/microblaze/allinsn.d: Likewise

diff --git a/gas/testsuite/gas/microblaze/allinsn.d b/gas/testsuite/gas/microblaze/allinsn.d
index c7854f18a3325437d88521b8aa0c5bc9ac990e60..ec140201548ce80d61a15beecc905ff45a8e4f25 100644 (file)
--- a/gas/testsuite/gas/microblaze/allinsn.d
+++ b/gas/testsuite/gas/microblaze/allinsn.d
@@ -25,3 +25,9 @@ Disassembly of section .text:
 
 00000018 <clz>:
   18:  900000e0        clz     r0, r0
+
+0000001c <mbar>:
+  1c:  b8420004        mbar    2
+
+00000020 <sleep>:
+  20:  ba020004        sleep

diff --git a/gas/testsuite/gas/microblaze/allinsn.s b/gas/testsuite/gas/microblaze/allinsn.s
index 0e4271d409cbafa348b44e3a10083f2a7536e707..582da1767313aa12170913a9b3b81dc5a0aaf3ce 100644 (file)
--- a/gas/testsuite/gas/microblaze/allinsn.s
+++ b/gas/testsuite/gas/microblaze/allinsn.s
@@ -28,4 +28,12 @@ swr:
     .global clz
 clz:
     clz r0,r0
+    .text
+    .global mbar
+mbar:
+    mbar 2
+    .text
+    .global sleep
+sleep:
+    sleep
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2efcdd22403d0abcb513e45c116f0779ac13addf..4b022da6729eab631745aacdd4ed8f0348c5dbf7 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2012-11-14  David Holsgrove  <david.holsgrove@xilinx.com>
+
+       * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
+       update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
+       and increase MAX_OPCODES.
+       (op_code_struct):  add mbar and sleep
+       * microblaze-opcm.h (microblaze_instr): add mbar
+       Define IMM_MBAR and IMM5_MBAR_MASK
+       * microblaze-dis.c: Add get_field_imm5_mbar
+       (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
+
 2012-11-14  Edgar E. Iglesias <edgar.iglesias@gmail.com>
 
        * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct):  add clz insn

diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
index bdbf8317d018f8f8cf96544cdb7f305217ebdaad..e204e36310db34650bf9b3bd662c6c74b94f193a 100644 (file)
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
@@ -64,6 +64,15 @@ get_field_imm5 (long instr)
   return (strdup (tmpstr));
 }
 
+static char *
+get_field_imm5_mbar (long instr)
+{
+  char tmpstr[25];
+
+  sprintf(tmpstr, "%d", (short)((instr & IMM5_MBAR_MASK) >> IMM_MBAR));
+  return(strdup(tmpstr));
+}
+
 static char *
 get_field_rfsl (long instr)
 {
@@ -374,6 +383,13 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
        case INST_TYPE_RD_IMM15:
          print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst));
          break;
+        /* For mbar insn.  */
+        case INST_TYPE_IMM5:
+          print_func (stream, "\t%s", get_field_imm5_mbar (inst));
+          break;
+        /* For mbar 16 or sleep insn.  */
+        case INST_TYPE_NONE:
+          break;
        /* For tuqula instruction */
        case INST_TYPE_RD:
          print_func (stream, "\t%s", get_field_rd (inst));

diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 132b95146565824895885b8cb3abc1474d590f5b..0447fc593377c8733ae1caeeeeee4e1d1beeda4d 100644 (file)
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -56,6 +56,9 @@
 /* New insn type for t*put.  */
 #define INST_TYPE_RFSL  19
 
+/* For mbar.  */
+#define INST_TYPE_IMM5 20
+
 #define INST_TYPE_NONE 25
 
 
@@ -76,8 +79,8 @@
 #define OPCODE_MASK_H2  0xFC1F0000  /* High 6 and bits 20-16.  */
 #define OPCODE_MASK_H12 0xFFFF0000  /* High 16.  */
 #define OPCODE_MASK_H4  0xFC0007FF  /* High 6 and low 11 bits.  */
-#define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last 
-                                      nibble of last byte for spr.  */
+#define OPCODE_MASK_H13S 0xFFE0E7F0 /* High 11 16:18 21:27 bits, 19:20 bits
+                                       and last nibble of last byte for spr.  */
 #define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last 
                                       nibble of last byte for spr.  */
 #define OPCODE_MASK_H34 0xFC00FFFF  /* High 6 and low 16 bits.  */
@@ -92,11 +95,13 @@
 
 /* New Mask for msrset, msrclr insns.  */
 #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
+/* Mask for mbar insn.  */
+#define OPCODE_MASK_HN 0xFF020004 /* High 16 bits and bits 14, 29.  */
 
 #define DELAY_SLOT 1
 #define NO_DELAY_SLOT 0
 
-#define MAX_OPCODES 285
+#define MAX_OPCODES 287
 
 struct op_code_struct
 {
@@ -395,6 +400,8 @@ struct op_code_struct
   {"necaputd",  INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd,  anyware_inst },
   {"tnecaputd", INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
   {"clz",       INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34,  clz,       special_inst },
+  {"mbar",      INST_TYPE_IMM5,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN,   mbar,      special_inst },
+  {"sleep",     INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 16.  */
   {"", 0, 0, 0, 0, 0, 0, 0, 0},
 };
 
@@ -412,5 +419,8 @@ char pvr_register_prefix[] = "rpvr";
 #define MIN_IMM15 ((int) 0x0000)
 #define MAX_IMM15 ((int) 0x7fff)
 
+#define MIN_IMM5  ((int) 0x00000000)
+#define MAX_IMM5  ((int) 0x0000001f)
+
 #endif /* MICROBLAZE_OPC */
 

diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 58e6fd45340bafb4858b5cec3936454cd8cbf114..867263e3968edac30dd98777321399af5cbeb708 100644 (file)
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -31,7 +31,7 @@ enum microblaze_instr
   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
   ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, 
-  wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd,
+  wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
   brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
   bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
@@ -122,6 +122,7 @@ enum microblaze_instr_type
 #define RA_LOW  16 /* Low bit for RA.  */
 #define RB_LOW  11 /* Low bit for RB.  */
 #define IMM_LOW  0 /* Low bit for immediate.  */
+#define IMM_MBAR 21 /* low bit for mbar instruction.  */
 
 #define RD_MASK 0x03E00000
 #define RA_MASK 0x001F0000
@@ -131,6 +132,9 @@ enum microblaze_instr_type
 /* Imm mask for barrel shifts.  */
 #define IMM5_MASK 0x0000001F
 
+/* Imm mask for mbar.  */
+#define IMM5_MBAR_MASK 0x03E00000
+
 /* FSL imm mask for get, put instructions.  */
 #define  RFSL_MASK 0x000000F