pwm: tegra: Allow 100 % duty cycle

To get 100 % duty cycle (always high), pulse width needs to be set to
256.

Signed-off-by: Victor(Weiguo) Pan <wpan@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 097658e0751b3f04a3bea0456e794981a710a0b1..2026eaa932ae576d4adcad8bbd84f8417df7a02d 100644 (file)
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -77,7 +77,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
         * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
         * nearest integer during division.
         */
-       c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
+       c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2;
        do_div(c, period_ns);
 
        val = (u32)c << PWM_DUTY_SHIFT;