ARM: dts: add CPU nodes for Exynos4 SoCs

Recent patch by Tomasz Figa ("irqchip: gic: Fix core ID calculation
when topology is read from DT") fixed GIC driver to filter cluster ID
from values returned by cpu_logical_map() for SoCs having registers
mapped without per-CPU banking making it is possible to add CPU nodes
for Exynos4 SoCs.  In case of Exynos SoCs these CPU nodes are also
required by future changes adding initialization of cpuidle states in
Exynos cpuidle driver through DT.

Tested on Origen board (Exynos4210 SoC) and Trats2 (Exynos4412 SoC).

Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 807bb5bf91fc84db70430ba17b7f507b6ca11a76..bcc9e63c8070194f5c0ab4e88b729159911ae107 100644 (file)
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,23 @@
                pinctrl2 = &pinctrl_2;
        };
 
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@900 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0x900>;
+               };
+
+               cpu@901 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0x901>;
+               };
+       };
+
        pmu_system_controller: system-controller@10020000 {
                clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
                                "clkout4", "clkout8", "clkout9";

diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 3c00e6ec93027f8ca410c1ee39b3b5d3200c3cd7..dd0a43ec56da905d64fc02f596b70d0ce92e67f3 100644 (file)
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -22,6 +22,23 @@
 / {
        compatible = "samsung,exynos4212", "samsung,exynos4";
 
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@A00 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0xA00>;
+               };
+
+               cpu@A01 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0xA01>;
+               };
+       };
+
        combiner: interrupt-controller@10440000 {
                samsung,combiner-nr = <18>;
        };

diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d8bc059e172ff1562ea4525cedc2ad14948a4bad..0f6ec93bb1d8a243d511dac4e2e42f6a794e9015 100644 (file)
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -22,6 +22,35 @@
 / {
        compatible = "samsung,exynos4412", "samsung,exynos4";
 
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@A00 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0xA00>;
+               };
+
+               cpu@A01 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0xA01>;
+               };
+
+               cpu@A02 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0xA02>;
+               };
+
+               cpu@A03 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0xA03>;
+               };
+       };
+
        combiner: interrupt-controller@10440000 {
                samsung,combiner-nr = <20>;
        };