powerpc/qe: set IReady in QE Microcode Upload

QE Microcode Initialization using qe_upload_microcode() does not work on
P1021 if the IRAM-Ready register is not set after the microcode upload. Add
a definition for the "I-RAM Ready" register and sets it upon microcode
upload completion.

Signed-off-by: Ioannis Kokkoris <ioannis.kokoris@siemens-enterprise.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
index 0edb6842b13ddc461c55c961170a4f0a9eaac4b0..61e8490786b808af0d93cb18729cb8b32c14bdec 100644 (file)
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -26,7 +26,9 @@
 struct qe_iram {
        __be32  iadd;           /* I-RAM Address Register */
        __be32  idata;          /* I-RAM Data Register */
-       u8      res0[0x78];
+       u8      res0[0x04];
+       __be32  iready;         /* I-RAM Ready Register */
+       u8      res1[0x70];
 } __attribute__ ((packed));
 
 /* QE Interrupt Controller */

diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index 5e0b6d511e14e8843cb5cfdbe181d992d0b1793e..229571a49391366ed5eea30c8ce5d9cf05b91606 100644 (file)
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -499,6 +499,7 @@ enum comm_dir {
 /* I-RAM */
 #define QE_IRAM_IADD_AIE       0x80000000      /* Auto Increment Enable */
 #define QE_IRAM_IADD_BADDR     0x00080000      /* Base Address */
+#define QE_IRAM_READY           0x80000000      /* Ready */
 
 /* UPC */
 #define UPGCR_PROTOCOL 0x80000000      /* protocol ul2 or pl2 */

diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 818e763f826509b78efdcd2ca216e395b8a52c43..b043675297299ceea7f317dfb1579c8a311aba98 100644 (file)
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -395,6 +395,9 @@ static void qe_upload_microcode(const void *base,
 
        for (i = 0; i < be32_to_cpu(ucode->count); i++)
                out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
+       
+       /* Set I-RAM Ready Register */
+       out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
 }
 
 /*