drm/i915/bxt: Sanitiy check the PHY lane power down status

We can check the power state of the PHY data and common lanes as
reported by the PHY. Do this in case we need to debug problems where the
PHY gets stuck in an unexpected state.

Note that I only check these when the lanes are expected to be powered
on purpose, since it's not clear at what point the PHY power/clock gates
things.

v2:
- Don't report the encoder as disabled when the sanity check fails.
  (Ville)

CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465825477-32671-1-git-send-email-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c8fd8b94deaf0e496325763035a949c94699bce3..e137ba471e91cd7243ffcf373228e599317304fe 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1279,6 +1279,15 @@ enum skl_disp_power_wells {
 #define BXT_P_CR_GT_DISP_PWRON         _MMIO(0x138090)
 #define   GT_DISPLAY_POWER_ON(phy)     (1 << (phy))
 
+#define _BXT_PHY_CTL_DDI_A             0x64C00
+#define _BXT_PHY_CTL_DDI_B             0x64C10
+#define _BXT_PHY_CTL_DDI_C             0x64C20
+#define   BXT_PHY_CMNLANE_POWERDOWN_ACK        (1 << 10)
+#define   BXT_PHY_LANE_POWERDOWN_ACK   (1 << 9)
+#define   BXT_PHY_LANE_ENABLED         (1 << 8)
+#define BXT_PHY_CTL(port)              _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
+                                                        _BXT_PHY_CTL_DDI_B)
+
 #define _PHY_CTL_FAMILY_EDP            0x64C80
 #define _PHY_CTL_FAMILY_DDI            0x64C90
 #define   COMMON_RESET_DIS             (1 << 31)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cb48b0d729e851b59b6c224d7f249929e2ca3660..ad3b0ee5e55b4073aadf946ab04ff0319c6e2ce9 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1342,6 +1342,14 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
        DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
 
 out:
+       if (ret && IS_BROXTON(dev_priv)) {
+               tmp = I915_READ(BXT_PHY_CTL(port));
+               if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
+                           BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
+                       DRM_ERROR("Port %c enabled but PHY powered down? "
+                                 "(PHY_CTL %08x)\n", port_name(port), tmp);
+       }
+
        intel_display_power_put(dev_priv, power_domain);
 
        return ret;
@@ -1745,6 +1753,8 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
                            enum dpio_phy phy)
 {
+       enum port port;
+
        if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
                return false;
 
@@ -1770,6 +1780,21 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
                return false;
        }
 
+       for_each_port_masked(port,
+                            phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
+                                               BIT(PORT_A)) {
+               u32 tmp = I915_READ(BXT_PHY_CTL(port));
+
+               if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
+                       DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
+                                        "for port %c powered down "
+                                        "(PHY_CTL %08x)\n",
+                                        phy, port_name(port), tmp);
+
+                       return false;
+               }
+       }
+
        return true;
 }