powerpc/perf: Fix handling of L3 events with bank == 1

Currently we reject events which have the L3 bank == 1, such as
0x000084918F, because the cache field is non-zero.

However that is incorrect, because although the bank is non-zero, the
value we would write into MMCRC is zero, and so we can count the event.

So fix the check to ignore the bank selector when checking whether the
cache selector is non-zero.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 3ad363da05f6637e109637cef260a7cf942ffd9a..fe2763b6e039cfc5773ba8255731a3f7d7228d78 100644 (file)
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -325,9 +325,10 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
                 * HV writable, and there is no API for guest kernels to modify
                 * it. The solution is for the hypervisor to initialise the
                 * field to zeroes, and for us to only ever allow events that
-                * have a cache selector of zero.
+                * have a cache selector of zero. The bank selector (bit 3) is
+                * irrelevant, as long as the rest of the value is 0.
                 */
-               if (cache)
+               if (cache & 0x7)
                        return -1;
 
        } else if (event & EVENT_IS_L1) {