[ARM] mv78xx0: enable eth2/eth3 on the mv78xx0 A0 development board
authorLennert Buytenhek <buytenh@wantstofly.org>
Fri, 20 Feb 2009 01:32:30 +0000 (02:32 +0100)
committerNicolas Pitre <nico@cam.org>
Fri, 20 Feb 2009 03:43:14 +0000 (22:43 -0500)
The A0 revision of the mv78xx0 development board has four ethernet
ports, with PHY IDs 8-11, whereas the Z0 version has two, with PHY
addresses 8-9.  This patch configures the third and fourth ethernet
port to use the PHY addresses on the A0 board to enable use of those
ports -- if we are running on a Z0 board, the ge10/11 setup code in
common.c will force these back to PHYless mode.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
arch/arm/mach-mv78xx0/db78x00-bp-setup.c

index 2e285bbb7bbd1ebb3368a0de746a524f7ca944fc..be0a59a6139eaeb4e685a1c2154d6c306e3ae7b9 100644 (file)
@@ -28,15 +28,11 @@ static struct mv643xx_eth_platform_data db78x00_ge01_data = {
 };
 
 static struct mv643xx_eth_platform_data db78x00_ge10_data = {
-       .phy_addr       = MV643XX_ETH_PHY_NONE,
-       .speed          = SPEED_1000,
-       .duplex         = DUPLEX_FULL,
+       .phy_addr       = MV643XX_ETH_PHY_ADDR(10),
 };
 
 static struct mv643xx_eth_platform_data db78x00_ge11_data = {
-       .phy_addr       = MV643XX_ETH_PHY_NONE,
-       .speed          = SPEED_1000,
-       .duplex         = DUPLEX_FULL,
+       .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
 };
 
 static struct mv_sata_platform_data db78x00_sata_data = {
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