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clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
author
Xing Zheng
<zhengxing@rock-chips.com>
Wed, 20 Apr 2016 11:12:10 +0000
(19:12 +0800)
committer
Heiko Stuebner
<heiko@sntech.de>
Mon, 25 Apr 2016 19:52:32 +0000
(21:52 +0200)
The gate bits of the i2c4 and i2c8 are incorrect due to the manual
error, we need to fix them.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3399.c
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diff --git
a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index e8f040be3feae650637095cdcb865d1386882b92..40b738460d474192dfc747f10c7c77f5d7fc2add 100644
(file)
--- a/
drivers/clk/rockchip/clk-rk3399.c
+++ b/
drivers/clk/rockchip/clk-rk3399.c
@@
-1401,11
+1401,11
@@
static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
- RK3399_PMU_CLKGATE_CON(0), 1
1
, GFLAGS),
+ RK3399_PMU_CLKGATE_CON(0), 1
0
, GFLAGS),
COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
- RK3399_PMU_CLKGATE_CON(0), 1
0
, GFLAGS),
+ RK3399_PMU_CLKGATE_CON(0), 1
1
, GFLAGS),
DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
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