drm/fsl-dcu: fix register initialization

The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for
Vybrid) whereas the register enumeration start from 1 (1-10 for
LS1021a and 1-9 for Vybrid). The loop started off from 0 for both
iterations and initialized the number of layers inclusive, which
is one layer too many.

All extensively written registers seem to be unassigned, it seems
that the write to those registers did not do any harm in practice.

Signed-off-by: Stefan Agner <stefan@agner.ch>

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index b36f815bd1d8599b2f73c474b232e02281cfae0b..7574db2da413cf54b60d670d0b1f7c3f673d0db3 100644 (file)
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -164,8 +164,8 @@ int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
                reg_num = LS1021A_LAYER_REG_NUM;
        else
                reg_num = VF610_LAYER_REG_NUM;
-       for (i = 0; i <= fsl_dev->soc->total_layer; i++) {
-               for (j = 0; j < reg_num; j++)
+       for (i = 0; i < fsl_dev->soc->total_layer; i++) {
+               for (j = 1; j <= reg_num; j++)
                        regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
        }
        regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,