drm/nouveau/disp/dp: support aux read interval during link training

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
index 3ca2d25b7f5e023b917dbd4dd246cd8e3fe64031..46563da2854e8d27715ee001051e279971df6cd4 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
@@ -48,7 +48,7 @@ struct dp_state {
        u8 version;
        struct nouveau_i2c_port *aux;
        int head;
-       u8  dpcd[4];
+       u8  dpcd[16];
        int link_nr;
        u32 link_bw;
        u8  stat[6];
@@ -149,7 +149,10 @@ dp_link_train_update(struct dp_state *dp, u32 delay)
 {
        int ret;
 
-       udelay(delay);
+       if (dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL])
+               mdelay(dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4);
+       else
+               udelay(delay);
 
        ret = nv_rdaux(dp->aux, DPCD_LS02, dp->stat, 6);
        if (ret)

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h b/drivers/gpu/drm/nouveau/core/engine/disp/dport.h
index 0e1bbd18ff6c4e4dc05d961d06a7f5e697643c07..4d375b759baf3b948ceb430c4594934fc3b19a47 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.h
@@ -2,15 +2,14 @@
 #define __NVKM_DISP_DPORT_H__
 
 /* DPCD Receiver Capabilities */
-#define DPCD_RC00                                                       0x00000
-#define DPCD_RC00_DPCD_REV                                                 0xff
-#define DPCD_RC01                                                       0x00001
-#define DPCD_RC01_MAX_LINK_RATE                                            0xff
+#define DPCD_RC00_DPCD_REV                                              0x00000
+#define DPCD_RC01_MAX_LINK_RATE                                         0x00001
 #define DPCD_RC02                                                       0x00002
 #define DPCD_RC02_ENHANCED_FRAME_CAP                                       0x80
 #define DPCD_RC02_MAX_LANE_COUNT                                           0x1f
 #define DPCD_RC03                                                       0x00003
 #define DPCD_RC03_MAX_DOWNSPREAD                                           0x01
+#define DPCD_RC0E_AUX_RD_INTERVAL                                       0x0000e
 
 /* DPCD Link Configuration */
 #define DPCD_LC00                                                       0x00100