ARM: dts: r8a7793: Add L2 cache-controller node

Add a device node for the L2 cache, and link the CPU node to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 9837f90f17182390046b75d6b3732c5bd665711c..b48215945241260102f007b9c28899d9549c240f 100644 (file)
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -51,6 +51,7 @@
                                           < 937500 1000000>,
                                           < 750000 1000000>,
                                           < 375000 1000000>;
+                       next-level-cache = <&L2_CA15>;
                };
        };
 
@@ -73,6 +74,12 @@
                };
        };
 
+       L2_CA15: cache-controller@0 {
+               compatible = "cache";
+               cache-unified;
+               cache-level = <2>;
+       };
+
        gic: interrupt-controller@f1001000 {
                compatible = "arm,gic-400";
                #interrupt-cells = <3>;