drm/i915: convert pipe timing definitions to transcoder

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6036d214994ceef0045ce3d6d216aa67be2a1466..b92e6bfbb97c556efac1d1f9c2ce4079341d3279 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -185,6 +185,8 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
        int vbl_start, vbl_end, htotal, vtotal;
        bool in_vbl = true;
        int ret = 0;
+       enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+                                                                     pipe);
 
        if (!i915_pipe_enabled(dev, pipe)) {
                DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
@@ -193,7 +195,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
        }
 
        /* Get vtotal. */
-       vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
+       vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 
        if (INTEL_INFO(dev)->gen >= 4) {
                /* No obvious pixelcount register. Only query vertical
@@ -213,13 +215,13 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
                 */
                position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 
-               htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
+               htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
                *vpos = position / htotal;
                *hpos = position - (*vpos * htotal);
        }
 
        /* Query vblank area. */
-       vbl = I915_READ(VBLANK(pipe));
+       vbl = I915_READ(VBLANK(cpu_transcoder));
 
        /* Test position against vblank region. */
        vbl_start = vbl & 0x1fff;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b33f05d53ad7624ba22bafa9076a9ccff6895ce5..be22aebe84f2b3dd3ab48cb91284354b606d33ad 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1568,14 +1568,14 @@
 #define _VSYNCSHIFT_B  0x61028
 
 
-#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
-#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
-#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
-#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
-#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
-#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
+#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
+#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
+#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
+#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
+#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
+#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
-#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
+#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
 
 /* VGA port control */
 #define ADPA                   0x61100

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d4ae5232fefa302b025c43c12993b51e33c44ceb..0f3187c516c52084c49f3607118dd78a4fbdcf9a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4488,6 +4488,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
        struct drm_device *dev = intel_crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum pipe pipe = intel_crtc->pipe;
+       enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
        uint32_t vsyncshift;
 
        if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
@@ -4501,25 +4502,25 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
        }
 
        if (INTEL_INFO(dev)->gen > 3)
-               I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
+               I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
 
-       I915_WRITE(HTOTAL(pipe),
+       I915_WRITE(HTOTAL(cpu_transcoder),
                   (adjusted_mode->crtc_hdisplay - 1) |
                   ((adjusted_mode->crtc_htotal - 1) << 16));
-       I915_WRITE(HBLANK(pipe),
+       I915_WRITE(HBLANK(cpu_transcoder),
                   (adjusted_mode->crtc_hblank_start - 1) |
                   ((adjusted_mode->crtc_hblank_end - 1) << 16));
-       I915_WRITE(HSYNC(pipe),
+       I915_WRITE(HSYNC(cpu_transcoder),
                   (adjusted_mode->crtc_hsync_start - 1) |
                   ((adjusted_mode->crtc_hsync_end - 1) << 16));
 
-       I915_WRITE(VTOTAL(pipe),
+       I915_WRITE(VTOTAL(cpu_transcoder),
                   (adjusted_mode->crtc_vdisplay - 1) |
                   ((adjusted_mode->crtc_vtotal - 1) << 16));
-       I915_WRITE(VBLANK(pipe),
+       I915_WRITE(VBLANK(cpu_transcoder),
                   (adjusted_mode->crtc_vblank_start - 1) |
                   ((adjusted_mode->crtc_vblank_end - 1) << 16));
-       I915_WRITE(VSYNC(pipe),
+       I915_WRITE(VSYNC(cpu_transcoder),
                   (adjusted_mode->crtc_vsync_start - 1) |
                   ((adjusted_mode->crtc_vsync_end - 1) << 16));
 
@@ -6481,12 +6482,12 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       int pipe = intel_crtc->pipe;
+       enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
        struct drm_display_mode *mode;
-       int htot = I915_READ(HTOTAL(pipe));
-       int hsync = I915_READ(HSYNC(pipe));
-       int vtot = I915_READ(VTOTAL(pipe));
-       int vsync = I915_READ(VSYNC(pipe));
+       int htot = I915_READ(HTOTAL(cpu_transcoder));
+       int hsync = I915_READ(HSYNC(cpu_transcoder));
+       int vtot = I915_READ(VTOTAL(cpu_transcoder));
+       int vsync = I915_READ(VSYNC(cpu_transcoder));
 
        mode = kzalloc(sizeof(*mode), GFP_KERNEL);
        if (!mode)
@@ -8946,12 +8947,12 @@ intel_display_capture_error_state(struct drm_device *dev)
 
                error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
                error->pipe[i].source = I915_READ(PIPESRC(i));
-               error->pipe[i].htotal = I915_READ(HTOTAL(i));
-               error->pipe[i].hblank = I915_READ(HBLANK(i));
-               error->pipe[i].hsync = I915_READ(HSYNC(i));
-               error->pipe[i].vtotal = I915_READ(VTOTAL(i));
-               error->pipe[i].vblank = I915_READ(VBLANK(i));
-               error->pipe[i].vsync = I915_READ(VSYNC(i));
+               error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
+               error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
+               error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
+               error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
+               error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
+               error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
        }
 
        return error;