CPU_GFNI_FLAGS, 0 },
{ STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
CPU_VAES_FLAGS, 0 },
+ { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
+ CPU_VPCLMULQDQ_FLAGS, 0 },
};
static const noarch_entry cpu_noarch[] =
@code{cet},
@code{gfni},
@code{vaes},
+@code{vpclmulqdq},
@code{prefetchwt1},
@code{clflushopt},
@code{se1},
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.gfni}
-@item @samp{.vaes}
+@item @samp{.vaes} @tab @samp{.vpclmulqdq}
@end multitable
Apart from the warning, there are only two other effects on
--- /dev/null
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX512F/VPCLMULQDQ insns (Intel disassembly)
+#source: avx512f_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f3 65 48 44 c9 ab[ ]*vpclmulqdq zmm1,zmm3,zmm1,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 65 48 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq zmm1,zmm3,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 65 48 44 4a 7f 7b[ ]*vpclmulqdq zmm1,zmm3,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 44 d2 ab[ ]*vpclmulqdq zmm2,zmm2,zmm2,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq zmm2,zmm2,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 44 52 7f 7b[ ]*vpclmulqdq zmm2,zmm2,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+#pass
--- /dev/null
+# Check 32bit AVX512F,VPCLMULQDQ WIG instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vpclmulqdq $0xab, %zmm2, %zmm1, %zmm6 # AVX512F,VPCLMULQDQ
+ vpclmulqdq $123, -123456(%esp,%esi,8), %zmm1, %zmm6 # AVX512F,VPCLMULQDQ
+ vpclmulqdq $123, 8128(%edx), %zmm1, %zmm6 # AVX512F,VPCLMULQDQ Disp8
+
+ .intel_syntax noprefix
+ vpclmulqdq zmm5, zmm1, zmm2, 0xab # AVX512F,VPCLMULQDQ
+ vpclmulqdq zmm5, zmm1, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512F,VPCLMULQDQ
+ vpclmulqdq zmm5, zmm1, ZMMWORD PTR [edx+8128], 123 # AVX512F,VPCLMULQDQ Disp8
--- /dev/null
+#as: -mevexwig=1
+#objdump: -dw -Mintel
+#name: i386 AVX512F/VPCLMULQDQ wig insns (Intel disassembly)
+#source: avx512f_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 f2 ab[ ]*vpclmulqdq zmm6,zmm1,zmm2,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq zmm6,zmm1,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 72 7f 7b[ ]*vpclmulqdq zmm6,zmm1,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 ea ab[ ]*vpclmulqdq zmm5,zmm1,zmm2,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 ac f4 c0 1d fe ff 7b[ ]*vpclmulqdq zmm5,zmm1,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 6a 7f 7b[ ]*vpclmulqdq zmm5,zmm1,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+#pass
--- /dev/null
+#as: -mevexwig=1
+#objdump: -dw
+#name: i386 AVX512F/VPCLMULQDQ wig insns
+#source: avx512f_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 f2 ab[ ]*vpclmulqdq \$0xab,%zmm2,%zmm1,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm1,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 72 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm1,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 ea ab[ ]*vpclmulqdq \$0xab,%zmm2,%zmm1,%zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 ac f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm1,%zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 6a 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm1,%zmm5
+#pass
--- /dev/null
+#as:
+#objdump: -dw
+#name: i386 AVX512F/VPCLMULQDQ insns
+#source: avx512f_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f3 65 48 44 c9 ab[ ]*vpclmulqdq \$0xab,%zmm1,%zmm3,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 65 48 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm3,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 65 48 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm3,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 44 d2 ab[ ]*vpclmulqdq \$0xab,%zmm2,%zmm2,%zmm2
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm2,%zmm2
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm2,%zmm2
+#pass
--- /dev/null
+# Check 32bit AVX512F,VPCLMULQDQ instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vpclmulqdq $0xab, %zmm1, %zmm3, %zmm1 # AVX512F,VPCLMULQDQ
+ vpclmulqdq $123, -123456(%esp,%esi,8), %zmm3, %zmm1 # AVX512F,VPCLMULQDQ
+ vpclmulqdq $123, 8128(%edx), %zmm3, %zmm1 # AVX512F,VPCLMULQDQ Disp8
+
+ .intel_syntax noprefix
+ vpclmulqdq zmm2, zmm2, zmm2, 0xab # AVX512F,VPCLMULQDQ
+ vpclmulqdq zmm2, zmm2, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512F,VPCLMULQDQ
+ vpclmulqdq zmm2, zmm2, ZMMWORD PTR [edx+8128], 123 # AVX512F,VPCLMULQDQ Disp8
--- /dev/null
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX512VL/VPCLMULQDQ insns (Intel disassembly)
+#source: avx512vl_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*c4 e3 69 44 da ab[ ]*vpclmulqdq xmm3,xmm2,xmm2,0xab
+[ ]*[a-f0-9]+:[ ]*c4 e3 69 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 69 44 9a f0 07 00 00 7b[ ]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 e1 ab[ ]*vpclmulqdq ymm4,ymm5,ymm1,0xab
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 a4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 a2 e0 0f 00 00 7b[ ]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 da ab[ ]*vpclmulqdq xmm3,xmm2,xmm2,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 5a 7f 7b[ ]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 e1 ab[ ]*vpclmulqdq ymm4,ymm5,ymm1,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 62 7f 7b[ ]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 51 44 db ab[ ]*vpclmulqdq xmm3,xmm5,xmm3,0xab
+[ ]*[a-f0-9]+:[ ]*c4 e3 51 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 51 44 9a f0 07 00 00 7b[ ]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 d2 ab[ ]*vpclmulqdq ymm2,ymm2,ymm2,0xab
+[ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 db ab[ ]*vpclmulqdq xmm3,xmm5,xmm3,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 5a 7f 7b[ ]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d2 ab[ ]*vpclmulqdq ymm2,ymm2,ymm2,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 52 7f 7b[ ]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[edx\+0xfe0\],0x7b
+#pass
--- /dev/null
+# Check 32bit AVX512VL,VPCLMULQDQ WIG instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vpclmulqdq $0xab, %xmm4, %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, -123456(%esp,%esi,8), %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 2032(%edx), %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ Disp8
+ vpclmulqdq $0xab, %ymm2, %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, -123456(%esp,%esi,8), %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 4064(%edx), %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ Disp8
+
+ {evex} vpclmulqdq $0xab, %xmm4, %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, -123456(%esp,%esi,8), %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 2032(%edx), %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ Disp8
+ {evex} vpclmulqdq $0xab, %ymm2, %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, -123456(%esp,%esi,8), %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 4064(%edx), %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ Disp8
+
+ .intel_syntax noprefix
+ vpclmulqdq xmm6, xmm4, xmm1, 0xab # AVX512VL,VPCLMULQDQ
+ vpclmulqdq xmm6, xmm4, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq xmm6, xmm4, XMMWORD PTR [edx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
+ vpclmulqdq ymm2, ymm4, ymm4, 0xab # AVX512VL,VPCLMULQDQ
+ vpclmulqdq ymm2, ymm4, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq ymm2, ymm4, YMMWORD PTR [edx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
+
+ {evex} vpclmulqdq xmm6, xmm4, xmm1, 0xab # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq xmm6, xmm4, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq xmm6, xmm4, XMMWORD PTR [edx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
+ {evex} vpclmulqdq ymm2, ymm4, ymm4, 0xab # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq ymm2, ymm4, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq ymm2, ymm4, YMMWORD PTR [edx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
--- /dev/null
+#as: -mevexwig=1
+#objdump: -dw -Mintel
+#name: i386 AVX512VL/VPCLMULQDQ wig insns (Intel disassembly)
+#source: avx512vl_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 cc ab[ ]*vpclmulqdq xmm1,xmm1,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 8a f0 07 00 00 7b[ ]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 da ab[ ]*vpclmulqdq ymm3,ymm5,ymm2,0xab
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9a e0 0f 00 00 7b[ ]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 cc ab[ ]*vpclmulqdq xmm1,xmm1,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 4a 7f 7b[ ]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 da ab[ ]*vpclmulqdq ymm3,ymm5,ymm2,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 5a 7f 7b[ ]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 f1 ab[ ]*vpclmulqdq xmm6,xmm4,xmm1,0xab
+[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b2 f0 07 00 00 7b[ ]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 d4 ab[ ]*vpclmulqdq ymm2,ymm4,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 f1 ab[ ]*vpclmulqdq xmm6,xmm4,xmm1,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 72 7f 7b[ ]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 d4 ab[ ]*vpclmulqdq ymm2,ymm4,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 52 7f 7b[ ]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
+#pass
--- /dev/null
+#as: -mevexwig=1
+#objdump: -dw
+#name: i386 AVX512VL/VPCLMULQDQ wig insns
+#source: avx512vl_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 cc ab[ ]*vpclmulqdq \$0xab,%xmm4,%xmm1,%xmm1
+[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm1,%xmm1
+[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 8a f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm1,%xmm1
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 da ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9a e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 cc ab[ ]*vpclmulqdq \$0xab,%xmm4,%xmm1,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm1,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm1,%xmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 da ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 5a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 f1 ab[ ]*vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
+[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
+[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b2 f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 d4 ab[ ]*vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 f1 ab[ ]*vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 72 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 d4 ab[ ]*vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
+#pass
--- /dev/null
+#as:
+#objdump: -dw
+#name: i386 AVX512VL/VPCLMULQDQ insns
+#source: avx512vl_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*c4 e3 69 44 da ab[ ]*vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 69 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 69 44 9a f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 e1 ab[ ]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 a4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 a2 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 da ab[ ]*vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 5a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 e1 ab[ ]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 62 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*c4 e3 51 44 db ab[ ]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 51 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 51 44 9a f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 d2 ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 db ab[ ]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 5a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d2 ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
+#pass
--- /dev/null
+# Check 32bit AVX512VL,VPCLMULQDQ instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vpclmulqdq $0xab, %xmm2, %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, -123456(%esp,%esi,8), %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 2032(%edx), %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ Disp8
+ vpclmulqdq $0xab, %ymm1, %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, -123456(%esp,%esi,8), %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 4064(%edx), %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ Disp8
+
+ {evex} vpclmulqdq $0xab, %xmm2, %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, -123456(%esp,%esi,8), %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 2032(%edx), %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ Disp8
+ {evex} vpclmulqdq $0xab, %ymm1, %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, -123456(%esp,%esi,8), %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 4064(%edx), %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ Disp8
+
+ .intel_syntax noprefix
+ vpclmulqdq xmm3, xmm5, xmm3, 0xab # AVX512VL,VPCLMULQDQ
+ vpclmulqdq xmm3, xmm5, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq xmm3, xmm5, XMMWORD PTR [edx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
+ vpclmulqdq ymm2, ymm2, ymm2, 0xab # AVX512VL,VPCLMULQDQ
+ vpclmulqdq ymm2, ymm2, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq ymm2, ymm2, YMMWORD PTR [edx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
+
+ {evex} vpclmulqdq xmm3, xmm5, xmm3, 0xab # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq xmm3, xmm5, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq xmm3, xmm5, XMMWORD PTR [edx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
+ {evex} vpclmulqdq ymm2, ymm2, ymm2, 0xab # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq ymm2, ymm2, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq ymm2, ymm2, YMMWORD PTR [edx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
run_dump_test "avx512vl_vaes-intel"
run_dump_test "avx512vl_vaes-wig1"
run_dump_test "avx512vl_vaes-wig1-intel"
+ run_dump_test "avx512f_vpclmulqdq"
+ run_dump_test "avx512f_vpclmulqdq-intel"
+ run_dump_test "avx512f_vpclmulqdq-wig1"
+ run_dump_test "avx512f_vpclmulqdq-wig1-intel"
+ run_dump_test "avx512vl_vpclmulqdq"
+ run_dump_test "avx512vl_vpclmulqdq-intel"
+ run_dump_test "avx512vl_vpclmulqdq-wig1"
+ run_dump_test "avx512vl_vpclmulqdq-wig1-intel"
run_dump_test "clzero"
run_dump_test "disassem"
run_dump_test "mwaitx-bdver4"
run_dump_test "gfni-intel"
run_dump_test "vaes"
run_dump_test "vaes-intel"
+ run_dump_test "vpclmulqdq"
+ run_dump_test "vpclmulqdq-intel"
run_list_test "avx512vl-1" "-al"
run_list_test "avx512vl-2" "-al"
run_dump_test "fpu-bad"
run_dump_test "x86-64-avx512vl_vaes-intel"
run_dump_test "x86-64-avx512vl_vaes-wig1"
run_dump_test "x86-64-avx512vl_vaes-wig1-intel"
+ run_dump_test "x86-64-avx512f_vpclmulqdq"
+ run_dump_test "x86-64-avx512f_vpclmulqdq-intel"
+ run_dump_test "x86-64-avx512f_vpclmulqdq-wig1"
+ run_dump_test "x86-64-avx512f_vpclmulqdq-wig1-intel"
+ run_dump_test "x86-64-avx512vl_vpclmulqdq"
+ run_dump_test "x86-64-avx512vl_vpclmulqdq-intel"
+ run_dump_test "x86-64-avx512vl_vpclmulqdq-wig1"
+ run_dump_test "x86-64-avx512vl_vpclmulqdq-wig1-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
run_dump_test "x86-64-gfni-intel"
run_dump_test "x86-64-vaes"
run_dump_test "x86-64-vaes-intel"
+ run_dump_test "x86-64-vpclmulqdq"
+ run_dump_test "x86-64-vpclmulqdq-intel"
run_dump_test "x86-64-fence-as-lock-add-yes"
run_dump_test "x86-64-fence-as-lock-add-no"
run_dump_test "x86-64-pr20141"
--- /dev/null
+#as:
+#objdump: -dw -Mintel
+#name: i386 VPCLMULQDQ insns (Intel disassembly)
+#source: vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 f4 ab[ ]*vpclmulqdq ymm6,ymm5,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 b2 e0 0f 00 00 7b[ ]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 f4 ab[ ]*vpclmulqdq ymm6,ymm5,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 b2 e0 0f 00 00 7b[ ]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+#pass
--- /dev/null
+#as:
+#objdump: -dw
+#name: i386 VPCLMULQDQ insns
+#source: vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 f4 ab[ ]*vpclmulqdq \$0xab,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 b2 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 f4 ab[ ]*vpclmulqdq \$0xab,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 b2 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
+#pass
--- /dev/null
+# Check VPCLMULQDQ instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vpclmulqdq $0xab, %ymm4, %ymm5, %ymm6
+ vpclmulqdq $123, -123456(%esp,%esi,8), %ymm5, %ymm6
+ vpclmulqdq $123, 4064(%edx), %ymm5, %ymm6
+
+ .intel_syntax noprefix
+ vpclmulqdq ymm6, ymm5, ymm4, 0xab
+ vpclmulqdq ymm6, ymm5, YMMWORD PTR [esp+esi*8-123456], 123
+ vpclmulqdq ymm6, ymm5, YMMWORD PTR [edx+4064], 123
--- /dev/null
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 AVX512F/VPCLMULQDQ insns (Intel disassembly)
+#source: x86-64-avx512f_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 03 45 40 44 d0 ab[ ]*vpclmulqdq zmm26,zmm23,zmm24,0xab
+[ ]*[a-f0-9]+:[ ]*62 23 45 40 44 94 f0 23 01 00 00 7b[ ]*vpclmulqdq zmm26,zmm23,ZMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 45 40 44 52 7f 7b[ ]*vpclmulqdq zmm26,zmm23,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 83 55 40 44 eb ab[ ]*vpclmulqdq zmm21,zmm21,zmm27,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 55 40 44 ac f0 34 12 00 00 7b[ ]*vpclmulqdq zmm21,zmm21,ZMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 55 40 44 6a 7f 7b[ ]*vpclmulqdq zmm21,zmm21,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
+#pass
--- /dev/null
+# Check 64bit AVX512F,VPCLMULQDQ WIG instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vpclmulqdq $0xab, %zmm19, %zmm20, %zmm22 # AVX512F,VPCLMULQDQ
+ vpclmulqdq $123, 0x123(%rax,%r14,8), %zmm20, %zmm22 # AVX512F,VPCLMULQDQ
+ vpclmulqdq $123, 8128(%rdx), %zmm20, %zmm22 # AVX512F,VPCLMULQDQ Disp8
+
+ .intel_syntax noprefix
+ vpclmulqdq zmm29, zmm28, zmm23, 0xab # AVX512F,VPCLMULQDQ
+ vpclmulqdq zmm29, zmm28, ZMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512F,VPCLMULQDQ
+ vpclmulqdq zmm29, zmm28, ZMMWORD PTR [rdx+8128], 123 # AVX512F,VPCLMULQDQ Disp8
--- /dev/null
+#as: -mevexwig=1
+#objdump: -dw -Mintel
+#name: x86_64 AVX512F/VPCLMULQDQ wig insns (Intel disassembly)
+#source: x86-64-avx512f_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 a3 dd 40 44 f3 ab[ ]*vpclmulqdq zmm22,zmm20,zmm19,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 dd 40 44 b4 f0 23 01 00 00 7b[ ]*vpclmulqdq zmm22,zmm20,ZMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 dd 40 44 72 7f 7b[ ]*vpclmulqdq zmm22,zmm20,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 23 9d 40 44 ef ab[ ]*vpclmulqdq zmm29,zmm28,zmm23,0xab
+[ ]*[a-f0-9]+:[ ]*62 23 9d 40 44 ac f0 34 12 00 00 7b[ ]*vpclmulqdq zmm29,zmm28,ZMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 9d 40 44 6a 7f 7b[ ]*vpclmulqdq zmm29,zmm28,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
+#pass
--- /dev/null
+#as: -mevexwig=1
+#objdump: -dw
+#name: x86_64 AVX512F/VPCLMULQDQ wig insns
+#source: x86-64-avx512f_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 a3 dd 40 44 f3 ab[ ]*vpclmulqdq \$0xab,%zmm19,%zmm20,%zmm22
+[ ]*[a-f0-9]+:[ ]*62 a3 dd 40 44 b4 f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%zmm20,%zmm22
+[ ]*[a-f0-9]+:[ ]*62 e3 dd 40 44 72 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm20,%zmm22
+[ ]*[a-f0-9]+:[ ]*62 23 9d 40 44 ef ab[ ]*vpclmulqdq \$0xab,%zmm23,%zmm28,%zmm29
+[ ]*[a-f0-9]+:[ ]*62 23 9d 40 44 ac f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%zmm28,%zmm29
+[ ]*[a-f0-9]+:[ ]*62 63 9d 40 44 6a 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm28,%zmm29
+#pass
--- /dev/null
+#as:
+#objdump: -dw
+#name: x86_64 AVX512F/VPCLMULQDQ insns
+#source: x86-64-avx512f_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 03 45 40 44 d0 ab[ ]*vpclmulqdq \$0xab,%zmm24,%zmm23,%zmm26
+[ ]*[a-f0-9]+:[ ]*62 23 45 40 44 94 f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%zmm23,%zmm26
+[ ]*[a-f0-9]+:[ ]*62 63 45 40 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm23,%zmm26
+[ ]*[a-f0-9]+:[ ]*62 83 55 40 44 eb ab[ ]*vpclmulqdq \$0xab,%zmm27,%zmm21,%zmm21
+[ ]*[a-f0-9]+:[ ]*62 a3 55 40 44 ac f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%zmm21,%zmm21
+[ ]*[a-f0-9]+:[ ]*62 e3 55 40 44 6a 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm21,%zmm21
+#pass
--- /dev/null
+# Check 64bit AVX512F,VPCLMULQDQ instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vpclmulqdq $0xab, %zmm24, %zmm23, %zmm26 # AVX512F,VPCLMULQDQ
+ vpclmulqdq $123, 0x123(%rax,%r14,8), %zmm23, %zmm26 # AVX512F,VPCLMULQDQ
+ vpclmulqdq $123, 8128(%rdx), %zmm23, %zmm26 # AVX512F,VPCLMULQDQ Disp8
+
+ .intel_syntax noprefix
+ vpclmulqdq zmm21, zmm21, zmm27, 0xab # AVX512F,VPCLMULQDQ
+ vpclmulqdq zmm21, zmm21, ZMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512F,VPCLMULQDQ
+ vpclmulqdq zmm21, zmm21, ZMMWORD PTR [rdx+8128], 123 # AVX512F,VPCLMULQDQ Disp8
--- /dev/null
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 AVX512VL/VPCLMULQDQ insns (Intel disassembly)
+#source: x86-64-avx512vl_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 ca ab[ ]*vpclmulqdq xmm25,xmm29,xmm18,0xab
+[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 15 00 44 4a 7f 7b[ ]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ea ab[ ]*vpclmulqdq ymm29,ymm18,ymm18,0xab
+[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ ]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 6d 20 44 6a 7f 7b[ ]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 ca ab[ ]*vpclmulqdq xmm25,xmm29,xmm18,0xab
+[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 15 00 44 4a 7f 7b[ ]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ea ab[ ]*vpclmulqdq ymm29,ymm18,ymm18,0xab
+[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ ]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 6d 20 44 6a 7f 7b[ ]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 dc ab[ ]*vpclmulqdq xmm19,xmm26,xmm20,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ ]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 2d 00 44 5a 7f 7b[ ]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 83 15 20 44 fb ab[ ]*vpclmulqdq ymm23,ymm29,ymm27,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 15 20 44 bc f0 34 12 00 00 7b[ ]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 15 20 44 7a 7f 7b[ ]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 dc ab[ ]*vpclmulqdq xmm19,xmm26,xmm20,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ ]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 2d 00 44 5a 7f 7b[ ]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 83 15 20 44 fb ab[ ]*vpclmulqdq ymm23,ymm29,ymm27,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 15 20 44 bc f0 34 12 00 00 7b[ ]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 15 20 44 7a 7f 7b[ ]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+#pass
--- /dev/null
+# Check 64bit AVX512VL,VPCLMULQDQ WIG instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vpclmulqdq $0xab, %xmm23, %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 0x123(%rax,%r14,8), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 2032(%rdx), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ Disp8
+ vpclmulqdq $0xab, %ymm19, %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 0x123(%rax,%r14,8), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 4064(%rdx), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ Disp8
+
+ {evex} vpclmulqdq $0xab, %xmm23, %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 0x123(%rax,%r14,8), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 2032(%rdx), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ Disp8
+ {evex} vpclmulqdq $0xab, %ymm19, %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 0x123(%rax,%r14,8), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 4064(%rdx), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ Disp8
+
+ .intel_syntax noprefix
+ vpclmulqdq xmm18, xmm22, xmm17, 0xab # AVX512VL,VPCLMULQDQ
+ vpclmulqdq xmm18, xmm22, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq xmm18, xmm22, XMMWORD PTR [rdx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
+ vpclmulqdq ymm26, ymm25, ymm23, 0xab # AVX512VL,VPCLMULQDQ
+ vpclmulqdq ymm26, ymm25, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq ymm26, ymm25, YMMWORD PTR [rdx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
+
+ {evex} vpclmulqdq xmm18, xmm22, xmm17, 0xab # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq xmm18, xmm22, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq xmm18, xmm22, XMMWORD PTR [rdx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
+ {evex} vpclmulqdq ymm26, ymm25, ymm23, 0xab # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq ymm26, ymm25, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq ymm26, ymm25, YMMWORD PTR [rdx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
--- /dev/null
+#as: -mevexwig=1
+#objdump: -dw -Mintel
+#name: x86_64 AVX512VL/VPCLMULQDQ wig insns (Intel disassembly)
+#source: x86-64-avx512vl_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 cf ab[ ]*vpclmulqdq xmm17,xmm21,xmm23,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 d5 00 44 4a 7f 7b[ ]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 fb ab[ ]*vpclmulqdq ymm23,ymm18,ymm19,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ ]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 ed 20 44 7a 7f 7b[ ]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 cf ab[ ]*vpclmulqdq xmm17,xmm21,xmm23,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 d5 00 44 4a 7f 7b[ ]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 fb ab[ ]*vpclmulqdq ymm23,ymm18,ymm19,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ ]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 ed 20 44 7a 7f 7b[ ]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 d1 ab[ ]*vpclmulqdq xmm18,xmm22,xmm17,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 cd 00 44 52 7f 7b[ ]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 d7 ab[ ]*vpclmulqdq ymm26,ymm25,ymm23,0xab
+[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 b5 20 44 52 7f 7b[ ]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 d1 ab[ ]*vpclmulqdq xmm18,xmm22,xmm17,0xab
+[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 e3 cd 00 44 52 7f 7b[ ]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 d7 ab[ ]*vpclmulqdq ymm26,ymm25,ymm23,0xab
+[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 b5 20 44 52 7f 7b[ ]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+#pass
--- /dev/null
+#as: -mevexwig=1
+#objdump: -dw
+#name: x86_64 AVX512VL/VPCLMULQDQ wig insns
+#source: x86-64-avx512vl_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 cf ab[ ]*vpclmulqdq \$0xab,%xmm23,%xmm21,%xmm17
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm21,%xmm17
+[ ]*[a-f0-9]+:[ ]*62 e3 d5 00 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm21,%xmm17
+[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 fb ab[ ]*vpclmulqdq \$0xab,%ymm19,%ymm18,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 e3 ed 20 44 7a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 cf ab[ ]*vpclmulqdq \$0xab,%xmm23,%xmm21,%xmm17
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm21,%xmm17
+[ ]*[a-f0-9]+:[ ]*62 e3 d5 00 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm21,%xmm17
+[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 fb ab[ ]*vpclmulqdq \$0xab,%ymm19,%ymm18,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 e3 ed 20 44 7a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 d1 ab[ ]*vpclmulqdq \$0xab,%xmm17,%xmm22,%xmm18
+[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm22,%xmm18
+[ ]*[a-f0-9]+:[ ]*62 e3 cd 00 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm22,%xmm18
+[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 d7 ab[ ]*vpclmulqdq \$0xab,%ymm23,%ymm25,%ymm26
+[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm25,%ymm26
+[ ]*[a-f0-9]+:[ ]*62 63 b5 20 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm25,%ymm26
+[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 d1 ab[ ]*vpclmulqdq \$0xab,%xmm17,%xmm22,%xmm18
+[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm22,%xmm18
+[ ]*[a-f0-9]+:[ ]*62 e3 cd 00 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm22,%xmm18
+[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 d7 ab[ ]*vpclmulqdq \$0xab,%ymm23,%ymm25,%ymm26
+[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm25,%ymm26
+[ ]*[a-f0-9]+:[ ]*62 63 b5 20 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm25,%ymm26
+#pass
--- /dev/null
+#as:
+#objdump: -dw
+#name: x86_64 AVX512VL/VPCLMULQDQ insns
+#source: x86-64-avx512vl_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 ca ab[ ]*vpclmulqdq \$0xab,%xmm18,%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 63 15 00 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ea ab[ ]*vpclmulqdq \$0xab,%ymm18,%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 63 6d 20 44 6a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 ca ab[ ]*vpclmulqdq \$0xab,%xmm18,%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 63 15 00 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ea ab[ ]*vpclmulqdq \$0xab,%ymm18,%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 63 6d 20 44 6a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 dc ab[ ]*vpclmulqdq \$0xab,%xmm20,%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 e3 2d 00 44 5a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 83 15 20 44 fb ab[ ]*vpclmulqdq \$0xab,%ymm27,%ymm29,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 a3 15 20 44 bc f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm29,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 e3 15 20 44 7a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 dc ab[ ]*vpclmulqdq \$0xab,%xmm20,%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 e3 2d 00 44 5a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 83 15 20 44 fb ab[ ]*vpclmulqdq \$0xab,%ymm27,%ymm29,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 a3 15 20 44 bc f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm29,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 e3 15 20 44 7a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm23
+#pass
--- /dev/null
+# Check 64bit AVX512VL,VPCLMULQDQ instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vpclmulqdq $0xab, %xmm18, %xmm29, %xmm25 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 0x123(%rax,%r14,8), %xmm29, %xmm25 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 2032(%rdx), %xmm29, %xmm25 # AVX512VL,VPCLMULQDQ Disp8
+ vpclmulqdq $0xab, %ymm18, %ymm18, %ymm29 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 0x123(%rax,%r14,8), %ymm18, %ymm29 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq $123, 4064(%rdx), %ymm18, %ymm29 # AVX512VL,VPCLMULQDQ Disp8
+
+ {evex} vpclmulqdq $0xab, %xmm18, %xmm29, %xmm25 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 0x123(%rax,%r14,8), %xmm29, %xmm25 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 2032(%rdx), %xmm29, %xmm25 # AVX512VL,VPCLMULQDQ Disp8
+ {evex} vpclmulqdq $0xab, %ymm18, %ymm18, %ymm29 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 0x123(%rax,%r14,8), %ymm18, %ymm29 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq $123, 4064(%rdx), %ymm18, %ymm29 # AVX512VL,VPCLMULQDQ Disp8
+
+ .intel_syntax noprefix
+ vpclmulqdq xmm19, xmm26, xmm20, 0xab # AVX512VL,VPCLMULQDQ
+ vpclmulqdq xmm19, xmm26, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq xmm19, xmm26, XMMWORD PTR [rdx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
+ vpclmulqdq ymm23, ymm29, ymm27, 0xab # AVX512VL,VPCLMULQDQ
+ vpclmulqdq ymm23, ymm29, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
+ vpclmulqdq ymm23, ymm29, YMMWORD PTR [rdx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
+
+ {evex} vpclmulqdq xmm19, xmm26, xmm20, 0xab # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq xmm19, xmm26, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq xmm19, xmm26, XMMWORD PTR [rdx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
+ {evex} vpclmulqdq ymm23, ymm29, ymm27, 0xab # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq ymm23, ymm29, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
+ {evex} vpclmulqdq ymm23, ymm29, YMMWORD PTR [rdx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
--- /dev/null
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 VPCLMULQDQ insns (Intel disassembly)
+#source: x86-64-vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 03 15 20 44 f4 ab[ ]*vpclmulqdq ymm30,ymm29,ymm28,0xab
+[ ]*[a-f0-9]+:[ ]*62 23 15 20 44 b4 f0 24 01 00 00 7b[ ]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x124\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 15 20 44 72 7f 7b[ ]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 03 15 20 44 f4 ab[ ]*vpclmulqdq ymm30,ymm29,ymm28,0xab
+[ ]*[a-f0-9]+:[ ]*62 23 15 20 44 b4 f0 34 12 00 00 7b[ ]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 15 20 44 72 7f 7b[ ]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+#pass
--- /dev/null
+#as:
+#objdump: -dw
+#name: x86_64 VPCLMULQDQ insns
+#source: x86-64-vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 03 15 20 44 f4 ab[ ]*vpclmulqdq \$0xab,%ymm28,%ymm29,%ymm30
+[ ]*[a-f0-9]+:[ ]*62 23 15 20 44 b4 f0 24 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x124\(%rax,%r14,8\),%ymm29,%ymm30
+[ ]*[a-f0-9]+:[ ]*62 63 15 20 44 72 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm30
+[ ]*[a-f0-9]+:[ ]*62 03 15 20 44 f4 ab[ ]*vpclmulqdq \$0xab,%ymm28,%ymm29,%ymm30
+[ ]*[a-f0-9]+:[ ]*62 23 15 20 44 b4 f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm29,%ymm30
+[ ]*[a-f0-9]+:[ ]*62 63 15 20 44 72 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm30
+#pass
--- /dev/null
+
+
+ .allow_index_reg
+ .text
+_start:
+ vpclmulqdq $0xab, %ymm28, %ymm29, %ymm30
+ vpclmulqdq $123, 0x124(%rax,%r14,8), %ymm29, %ymm30
+ vpclmulqdq $123, 4064(%rdx), %ymm29, %ymm30
+
+ .intel_syntax noprefix
+ vpclmulqdq ymm30, ymm29, ymm28, 0xab
+ vpclmulqdq ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234], 123
+ vpclmulqdq ymm30, ymm29, YMMWORD PTR [rdx+4064], 123
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_0F3A42) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3A43) },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_0F3A44) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F3A43_P_2) },
},
+ /* PREFIX_EVEX_0F3A44 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpclmulqdq", { XM, Vex, EXx, Ib }, 0 },
+ },
/* PREFIX_EVEX_0F3A50 */
{
{ Bad_Opcode },
PREFIX_EVEX_0F3A3F,
PREFIX_EVEX_0F3A42,
PREFIX_EVEX_0F3A43,
+ PREFIX_EVEX_0F3A44,
PREFIX_EVEX_0F3A50,
PREFIX_EVEX_0F3A51,
PREFIX_EVEX_0F3A54,
VEX_LEN_0F3A38_P_2,
VEX_LEN_0F3A39_P_2,
VEX_LEN_0F3A41_P_2,
- VEX_LEN_0F3A44_P_2,
VEX_LEN_0F3A46_P_2,
VEX_LEN_0F3A60_P_2,
VEX_LEN_0F3A61_P_2,
VEX_W_0F3A40_P_2,
VEX_W_0F3A41_P_2,
VEX_W_0F3A42_P_2,
- VEX_W_0F3A44_P_2,
VEX_W_0F3A46_P_2,
VEX_W_0F3A48_P_2,
VEX_W_0F3A49_P_2,
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
+ { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
},
/* PREFIX_VEX_0F3A46 */
{ VEX_W_TABLE (VEX_W_0F3A41_P_2) },
},
- /* VEX_LEN_0F3A44_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
- },
-
/* VEX_LEN_0F3A46_P_2 */
{
{ Bad_Opcode },
/* VEX_W_0F3A42_P_2 */
{ "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
},
- {
- /* VEX_W_0F3A44_P_2 */
- { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
- },
{
/* VEX_W_0F3A46_P_2 */
{ "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
"CpuGFNI" },
{ "CPU_VAES_FLAGS",
"CpuVAES" },
+ { "CPU_VPCLMULQDQ_FLAGS",
+ "CpuVPCLMULQDQ" },
{ "CPU_ANY_X87_FLAGS",
"CPU_ANY_287_FLAGS|Cpu8087" },
{ "CPU_ANY_287_FLAGS",
BITFIELD (CpuCET),
BITFIELD (CpuGFNI),
BITFIELD (CpuVAES),
+ BITFIELD (CpuVPCLMULQDQ),
BITFIELD (CpuRegMMX),
BITFIELD (CpuRegXMM),
BITFIELD (CpuRegYMM),
CpuGFNI,
/* VAES instructions required */
CpuVAES,
+ /* VPCLMULQDQ instructions required */
+ CpuVPCLMULQDQ,
/* MMX register support required */
CpuRegMMX,
/* XMM register support required */
/* If you get a compiler error for zero width of the unused field,
comment it out. */
-#define CpuUnused (CpuMax + 1)
+ #define CpuUnused (CpuMax + 1)
/* We can check if an instruction is available with array instead
of bitfield. */
unsigned int cpucet:1;
unsigned int cpugfni:1;
unsigned int cpuvaes:1;
+ unsigned int cpuvpclmulqdq:1;
unsigned int cpuregmmx:1;
unsigned int cpuregxmm:1;
unsigned int cpuregymm:1;
sha256msg1, 2, 0xf38cc, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
sha256msg2, 2, 0xf38cd, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
+// VPCLMULQDQ instructions
+
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+
+// VPCLMULQDQ instructions end
+
// AVX512F instructions.
kandnw, 3, 0x42, None, 1, CpuAVX512F, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
// AVX512 + VAES instructions end
+// AVX512 + VPCLMULQDQ instructions
+
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|EVex=1|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ|CpuAVX512VL, Modrm|EVex=2|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ|CpuAVX512VL, Modrm|EVex=3|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
+
+// AVX512 + VPCLMULQDQ instructions end
+
// CLZERO instructions
clzero, 0, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
projects / deliverable / binutils-gdb.git / commitdiff
