From: Andrew Burgess Date: Wed, 30 Mar 2016 17:13:31 +0000 (+0100) Subject: opcodes/arc: Comment and whitespace fixes in opcode table X-Git-Url: http://drtracing.org/?a=commitdiff_plain;ds=sidebyside;h=0a106562e3ab2582854b28d82025ccd5e5d1ad00;p=deliverable%2Fbinutils-gdb.git opcodes/arc: Comment and whitespace fixes in opcode table Add a new comment, and clean up some whitespace issues in the instruction table. opcode/ChangeLog: * arc-nps400-tbl.h: Add a header comment, and fix some whitespace issues. No functional changes. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e0e8a18fd7..59b49416ea 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2016-03-30 Andrew Burgess + + * arc-nps400-tbl.h: Add a header comment, and fix some whitespace + issues. No functional changes. + 2016-03-30 Claudiu Zissulescu * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0) diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h index 4b715f966d..493c5b6584 100644 --- a/opcodes/arc-nps400-tbl.h +++ b/opcodes/arc-nps400-tbl.h @@ -1,11 +1,13 @@ +/**** Bit Manipulation Instructions ****/ + /* movl<.cl> */ -{ "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, -{ "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, +{ "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, +{ "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, /* movl<.cl> */ -{ "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, -{ "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, +{ "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, +{ "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, /* movb<.f><.cl> */ -{ "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, -{ "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }}, +{ "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, +{ "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},