From: navin patidar Date: Sun, 7 Sep 2014 11:07:43 +0000 (+0530) Subject: staging: rtl8188eu: Rework function phy_PathA_RxIQK() X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=0fdd0c324826381213c2b334e8d4ccfad314d66b;p=deliverable%2Flinux.git staging: rtl8188eu: Rework function phy_PathA_RxIQK() Rename CamelCase function name and variables. Remove unnecessary debugging messages. Signed-off-by: navin patidar Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c b/drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c index 9770106a605f..186b718670fc 100644 --- a/drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c +++ b/drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c @@ -356,8 +356,7 @@ void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt) dm_odm->RFCalibrateInfo.TXPowercount = 0; } -/* 1 7. IQK */ -#define MAX_TOLERANCE 5 +#define MAX_TOLERANCE 5 static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ phy_PathA_IQK_8188E(struct adapter *adapt, bool configPathB) @@ -407,18 +406,15 @@ phy_PathA_IQK_8188E(struct adapter *adapt, bool configPathB) return result; } -static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ -phy_PathA_RxIQK(struct adapter *adapt, bool configPathB) +static u8 phy_path_a_rx_iqk(struct adapter *adapt, bool configPathB) { - u32 regeac, regE94, regE9C, regEA4, u4tmp; + u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u4tmp; u8 result = 0x00; - struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt); - struct odm_dm_struct *dm_odm = &pHalData->odmpriv; - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); + struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt); + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; /* 1 Get TXIMR setting */ /* modify RXIQK mode table */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); phy_set_rf_reg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); phy_set_rf_reg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); @@ -442,45 +438,34 @@ phy_PathA_RxIQK(struct adapter *adapt, bool configPathB) phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000); /* LO calibration setting */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); /* One shot, path A LOK & IQK */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - /* delay x ms */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("Delay %d ms for One shot, path A LOK & IQK.\n", - IQK_DELAY_TIME_88E)); + /* delay x ms */ mdelay(IQK_DELAY_TIME_88E); - /* Check failed */ - regeac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("0xeac = 0x%x\n", regeac)); - regE94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("0xe94 = 0x%x\n", regE94)); - regE9C = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("0xe9c = 0x%x\n", regE9C)); + /* Check failed */ + reg_eac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); + reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); + reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord); - if (!(regeac & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42)) + if (!(reg_eac & BIT28) && + (((reg_e94 & 0x03FF0000)>>16) != 0x142) && + (((reg_e9c & 0x03FF0000)>>16) != 0x42)) result |= 0x01; - else /* if Tx not OK, ignore Rx */ + else /* if Tx not OK, ignore Rx */ return result; - u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); + u4tmp = 0x80007C00 | (reg_e94&0x3FF0000) | ((reg_e9c&0x3FF0000) >> 16); phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, u4tmp); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", phy_query_bb_reg(adapt, rTx_IQK, bMaskDWord), u4tmp)); /* 1 RX IQK */ /* modify RXIQK mode table */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("Path-A Rx IQK modify RXIQK mode table 2!\n")); phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); phy_set_rf_reg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); phy_set_rf_reg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); @@ -498,39 +483,30 @@ phy_PathA_RxIQK(struct adapter *adapt, bool configPathB) phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f); /* LO calibration setting */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - /* One shot, path A LOK & IQK */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - /* delay x ms */ - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ mdelay(IQK_DELAY_TIME_88E); /* Check failed */ - regeac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regeac)); - regE94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94)); - regE9C = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C)); - regEA4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord); - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); + reg_eac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); + reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); + reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord); + reg_ea4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord); /* reload RF 0xdf */ phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); phy_set_rf_reg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); - if (!(regeac & BIT27) && /* if Tx is OK, check whether Rx is OK */ - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regeac & 0x03FF0000)>>16) != 0x36)) + if (!(reg_eac & BIT27) && /* if Tx is OK, check whether Rx is OK */ + (((reg_ea4 & 0x03FF0000)>>16) != 0x132) && + (((reg_eac & 0x03FF0000)>>16) != 0x36)) result |= 0x02; else - ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); + ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("Path A Rx IQK fail!!\n")); return result; } @@ -1021,7 +997,7 @@ static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t, } for (i = 0; i < retryCount; i++) { - PathAOK = phy_PathA_RxIQK(adapt, is2t); + PathAOK = phy_path_a_rx_iqk(adapt, is2t); if (PathAOK == 0x03) { ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); result[t][2] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;