From: Thiemo Seufer Date: Tue, 7 Aug 2001 12:36:13 +0000 (+0000) Subject: * mips-dis.c (print_insn_arg): Don't use software integer registers X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=21d34b1c68bbfe3fcf4b55fbcb5c2adc3bb24c34;p=deliverable%2Fbinutils-gdb.git * mips-dis.c (print_insn_arg): Don't use software integer registers for coprocessor registers. (_print_insn_mips): Get distinction between old ABI and new ABI right. --- diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 17a72d57e9..21416f9bab 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2001-07-21 Thiemo Seufer + + * mips/lb.d: Reflect disassembler output fixes. + * mips/mips32.d: Likewise. + * mips/mips64.d: Likewise. Typo. + * mips/sb.d: Likewise. + * mips/trunc.d: Likewise. + 2001-08-04 H.J. Lu * gas/cris/operand-err-1.s: Updated. diff --git a/gas/testsuite/gas/mips/lb.d b/gas/testsuite/gas/mips/lb.d index 9bb9801f5e..f7ff718741 100644 --- a/gas/testsuite/gas/mips/lb.d +++ b/gas/testsuite/gas/mips/lb.d @@ -388,8 +388,8 @@ Disassembly of section .text: 0+0378 <[^>]*> lw a0,0\(zero\) 0+037c <[^>]*> lwl a0,0\(zero\) 0+0380 <[^>]*> lwr a0,0\(zero\) -0+0384 <[^>]*> lwc0 a0,0\(zero\) +0+0384 <[^>]*> lwc0 \$4,0\(zero\) 0+0388 <[^>]*> lwc1 \$f4,0\(zero\) -0+038c <[^>]*> lwc2 a0,0\(zero\) -0+0390 <[^>]*> lwc3 a0,0\(zero\) +0+038c <[^>]*> lwc2 \$4,0\(zero\) +0+0390 <[^>]*> lwc3 \$4,0\(zero\) ... diff --git a/gas/testsuite/gas/mips/mips32.d b/gas/testsuite/gas/mips/mips32.d index 754a5ff0a8..fb6f9cd43e 100644 --- a/gas/testsuite/gas/mips/mips32.d +++ b/gas/testsuite/gas/mips/mips32.d @@ -26,15 +26,15 @@ Disassembly of section .text: 0+0040 <[^>]*> 00000000 nop 0+0044 <[^>]*> 4903ffee bc2tl 0+0000 0+0048 <[^>]*> 00000000 nop -0+004c <[^>]*> 48411000 cfc2 at,v0 +0+004c <[^>]*> 48411000 cfc2 at,\$2 0+0050 <[^>]*> 4b234567 c2 0x1234567 -0+0054 <[^>]*> 48c21800 ctc2 v0,v1 -0+0058 <[^>]*> 48032000 mfc2 v1,a0 -0+005c <[^>]*> 48042800 mfc2 a0,a1 -0+0060 <[^>]*> 48053007 mfc2 a1,a2,7 -0+0064 <[^>]*> 48863800 mtc2 a2,a3 -0+0068 <[^>]*> 48874000 mtc2 a3,t0 -0+006c <[^>]*> 48884807 mtc2 t0,t1,7 +0+0054 <[^>]*> 48c21800 ctc2 v0,\$3 +0+0058 <[^>]*> 48032000 mfc2 v1,\$4 +0+005c <[^>]*> 48042800 mfc2 a0,\$5 +0+0060 <[^>]*> 48053007 mfc2 a1,\$6,7 +0+0064 <[^>]*> 48863800 mtc2 a2,\$7 +0+0068 <[^>]*> 48874000 mtc2 a3,\$8 +0+006c <[^>]*> 48884807 mtc2 t0,\$9,7 0+0070 <[^>]*> bc250000 cache 0x5,0\(at\) 0+0074 <[^>]*> bc457fff cache 0x5,32767\(v0\) 0+0078 <[^>]*> bc658000 cache 0x5,-32768\(v1\) diff --git a/gas/testsuite/gas/mips/mips64.d b/gas/testsuite/gas/mips/mips64.d index 5793d29c49..dcb8cd3771 100644 --- a/gas/testsuite/gas/mips/mips64.d +++ b/gas/testsuite/gas/mips/mips64.d @@ -2,16 +2,16 @@ #name: MIPS MIPS64 instructions #as: -mips64 -# Check MIPS32 instruction assembly +# Check MIPS64 instruction assembly .*: +file format .*mips.* Disassembly of section .text: 0+0000 <[^>]*> 70410825 dclo at,v0 0+0004 <[^>]*> 70831824 dclz v1,a0 -0+0008 <[^>]*> 48232000 dmfc2 v1,a0 -0+000c <[^>]*> 48242800 dmfc2 a0,a1 -0+0010 <[^>]*> 48253007 dmfc2 a1,a2,7 -0+0014 <[^>]*> 48a63800 dmtc2 a2,a3 -0+0018 <[^>]*> 48a74000 dmtc2 a3,t0 -0+001c <[^>]*> 48a84807 dmtc2 t0,t1,7 +0+0008 <[^>]*> 48232000 dmfc2 v1,\$4 +0+000c <[^>]*> 48242800 dmfc2 a0,\$5 +0+0010 <[^>]*> 48253007 dmfc2 a1,\$6,7 +0+0014 <[^>]*> 48a63800 dmtc2 a2,\$7 +0+0018 <[^>]*> 48a74000 dmtc2 a3,\$8 +0+001c <[^>]*> 48a84807 dmtc2 t0,\$9,7 diff --git a/gas/testsuite/gas/mips/sb.d b/gas/testsuite/gas/mips/sb.d index 85b2ece26b..3c839db2e4 100644 --- a/gas/testsuite/gas/mips/sb.d +++ b/gas/testsuite/gas/mips/sb.d @@ -386,10 +386,10 @@ Disassembly of section .text: 0+0370 <[^>]*> sw a1,4\(zero\) 0+0374 <[^>]*> sh a0,0\(zero\) 0+0378 <[^>]*> sw a0,0\(zero\) -0+037c <[^>]*> swc0 a0,0\(zero\) +0+037c <[^>]*> swc0 \$4,0\(zero\) 0+0380 <[^>]*> swc1 \$f4,0\(zero\) -0+0384 <[^>]*> swc2 a0,0\(zero\) -0+0388 <[^>]*> swc3 a0,0\(zero\) +0+0384 <[^>]*> swc2 \$4,0\(zero\) +0+0388 <[^>]*> swc3 \$4,0\(zero\) 0+038c <[^>]*> swc1 \$f4,0\(zero\) 0+0390 <[^>]*> swl a0,0\(zero\) 0+0394 <[^>]*> swr a0,0\(zero\) diff --git a/gas/testsuite/gas/mips/trunc.d b/gas/testsuite/gas/mips/trunc.d index 0087c02f13..324650eb31 100644 --- a/gas/testsuite/gas/mips/trunc.d +++ b/gas/testsuite/gas/mips/trunc.d @@ -7,23 +7,23 @@ .*: +file format .*mips.* Disassembly of section .text: -0+0000 <[^>]*> cfc1 a0,ra -0+0004 <[^>]*> cfc1 a0,ra +0+0000 <[^>]*> cfc1 a0,\$31 +0+0004 <[^>]*> cfc1 a0,\$31 0+0008 <[^>]*> nop 0+000c <[^>]*> ori at,a0,0x3 0+0010 <[^>]*> xori at,at,0x2 -0+0014 <[^>]*> ctc1 at,ra +0+0014 <[^>]*> ctc1 at,\$31 0+0018 <[^>]*> nop 0+001c <[^>]*> cvt.w.d \$f4,\$f6 -0+0020 <[^>]*> ctc1 a0,ra +0+0020 <[^>]*> ctc1 a0,\$31 0+0024 <[^>]*> nop -0+0028 <[^>]*> cfc1 a0,ra -0+002c <[^>]*> cfc1 a0,ra +0+0028 <[^>]*> cfc1 a0,\$31 +0+002c <[^>]*> cfc1 a0,\$31 0+0030 <[^>]*> nop 0+0034 <[^>]*> ori at,a0,0x3 0+0038 <[^>]*> xori at,at,0x2 -0+003c <[^>]*> ctc1 at,ra +0+003c <[^>]*> ctc1 at,\$31 0+0040 <[^>]*> nop 0+0044 <[^>]*> cvt.w.s \$f4,\$f6 -0+0048 <[^>]*> ctc1 a0,ra +0+0048 <[^>]*> ctc1 a0,\$31 0+004c <[^>]*> nop diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index bf3e14a595..302768751a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2001-07-21 Thiemo Seufer + + * mips-dis.c (print_insn_arg): Don't use software integer registers + for coprocessor registers. + (get_mips_isa): Removed. + (is_newabi): New function, checks if NewABI is used. + (_print_insn_mips): Get distinction between old ABI and new ABI right. + 2001-08-01 Christian Groessler * z8kgen.c: Fixed indentation of opt[] array. Include stdio.h to diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 3d737f67c3..97f263d4df 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -256,13 +256,13 @@ print_insn_arg (d, l, pc, info) break; case 'E': - (*info->fprintf_func) (info->stream, "%s", - reg_names[(l >> OP_SH_RT) & OP_MASK_RT]); + (*info->fprintf_func) (info->stream, "$%d", + (l >> OP_SH_RT) & OP_MASK_RT); break; case 'G': - (*info->fprintf_func) (info->stream, "%s", - reg_names[(l >> OP_SH_RD) & OP_MASK_RD]); + (*info->fprintf_func) (info->stream, "$%d", + (l >> OP_SH_RD) & OP_MASK_RD); break; case 'N': @@ -395,17 +395,19 @@ mips_isa_type (mach, isa, cputype) } } -/* Figure out ISA from disassemble_info data */ +/* Check if the object uses NewABI conventions. */ static int -get_mips_isa (info) - struct disassemble_info *info; +is_newabi(header) + Elf_Internal_Ehdr *header; { - int isa; - int cpu; + if ((header->e_flags + & (E_MIPS_ABI_EABI32 | E_MIPS_ABI_EABI64 | EF_MIPS_ABI2)) != 0 + || (header->e_ident[EI_CLASS] == ELFCLASS64 + && (header->e_flags & E_MIPS_ABI_O64) == 0)) + return 1; - mips_isa_type (info->mach, &isa, &cpu); - return isa; + return 0; } /* Print the mips instruction at address MEMADDR in debugged memory, @@ -522,14 +524,16 @@ _print_insn_mips (memaddr, info, endianness) #endif /* Use mips64_reg_names for new ABI. */ - if (info->flavour == bfd_target_elf_flavour - && info->symbols != NULL - && (((get_mips_isa(info) | INSN_ISA_MASK) & ISA_MIPS2) != 0) - && ((elf_elfheader (bfd_asymbol_bfd(*(info->symbols)))->e_flags - & EF_MIPS_ABI2) != 0)) - reg_names = mips64_reg_names; - else - reg_names = mips32_reg_names; + reg_names = mips32_reg_names; + + if (info->flavour == bfd_target_elf_flavour && info->symbols != NULL) + { + Elf_Internal_Ehdr *header; + + header = elf_elfheader(bfd_asymbol_bfd(*(info->symbols))); + if (is_newabi(header)) + reg_names = mips64_reg_names; + } status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); if (status == 0)