From: Ben Skeggs Date: Wed, 14 Jan 2015 04:35:35 +0000 (+1000) Subject: drm/nouveau/bar: namespace + nvidia gpu names (no binary change) X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=245dcfe96f6900dbf64e48a350badf4c90fabc2e;p=deliverable%2Flinux.git drm/nouveau/bar: namespace + nvidia gpu names (no binary change) The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs --- diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h index 0b5a1e4dff48..18e5edde08bd 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h @@ -137,6 +137,8 @@ #define nouveau_vm_put nvkm_vm_put #define nouveau_vm_map nvkm_vm_map #define nouveau_vm_unmap nvkm_vm_unmap +#define nouveau_vm_new nvkm_vm_new +#define nouveau_vm_ref nvkm_vm_ref #define nouveau_instmem nvkm_instmem #define nouveau_instobj nvkm_instobj #define nouveau_mem nvkm_mem diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h index 960e33a30819..c7a007b8bc10 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h @@ -1,37 +1,33 @@ -#ifndef __NOUVEAU_BAR_H__ -#define __NOUVEAU_BAR_H__ - +#ifndef __NVKM_BAR_H__ +#define __NVKM_BAR_H__ #include -#include - -struct nouveau_mem; -struct nouveau_vma; +struct nvkm_mem; +struct nvkm_vma; -struct nouveau_bar { - struct nouveau_subdev base; +struct nvkm_bar { + struct nvkm_subdev base; - int (*alloc)(struct nouveau_bar *, struct nouveau_object *, - struct nouveau_mem *, struct nouveau_object **); + int (*alloc)(struct nvkm_bar *, struct nvkm_object *, + struct nvkm_mem *, struct nvkm_object **); - int (*kmap)(struct nouveau_bar *, struct nouveau_mem *, - u32 flags, struct nouveau_vma *); - int (*umap)(struct nouveau_bar *, struct nouveau_mem *, - u32 flags, struct nouveau_vma *); - void (*unmap)(struct nouveau_bar *, struct nouveau_vma *); - void (*flush)(struct nouveau_bar *); + int (*kmap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags, + struct nvkm_vma *); + int (*umap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags, + struct nvkm_vma *); + void (*unmap)(struct nvkm_bar *, struct nvkm_vma *); + void (*flush)(struct nvkm_bar *); /* whether the BAR supports to be ioremapped WC or should be uncached */ bool iomap_uncached; }; -static inline struct nouveau_bar * -nouveau_bar(void *obj) +static inline struct nvkm_bar * +nvkm_bar(void *obj) { - return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_BAR); + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BAR); } -extern struct nouveau_oclass nv50_bar_oclass; -extern struct nouveau_oclass nvc0_bar_oclass; -extern struct nouveau_oclass gk20a_bar_oclass; - +extern struct nvkm_oclass nv50_bar_oclass; +extern struct nvkm_oclass gf100_bar_oclass; +extern struct nvkm_oclass gk20a_bar_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ramht.c b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c index 0a382d0975b0..ebd4d15479bd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ramht.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c @@ -20,6 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ #include +#include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 915ba957f075..29dbe1693480 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -77,7 +77,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; #if 0 @@ -121,7 +121,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index 2a6fc7f6fd85..5e4608fba660 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -77,7 +77,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; @@ -110,7 +110,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; @@ -143,7 +143,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; @@ -175,7 +175,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; @@ -208,7 +208,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; @@ -240,7 +240,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; @@ -272,7 +272,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; @@ -305,7 +305,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; @@ -337,7 +337,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index b2225ec499b1..a488b30304cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -77,7 +77,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; @@ -111,7 +111,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; @@ -145,7 +145,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; @@ -201,7 +201,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; @@ -235,7 +235,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; @@ -269,7 +269,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; @@ -302,7 +302,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild index 922454f97de2..1ab554a0b5e0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild @@ -1,4 +1,4 @@ nvkm-y += nvkm/subdev/bar/base.o nvkm-y += nvkm/subdev/bar/nv50.o -nvkm-y += nvkm/subdev/bar/nvc0.o +nvkm-y += nvkm/subdev/bar/gf100.o nvkm-y += nvkm/subdev/bar/gk20a.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c index 1b37afe4a4ea..3502d00122ef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c @@ -21,33 +21,30 @@ * * Authors: Ben Skeggs */ +#include "priv.h" -#include - +#include #include #include -#include "priv.h" - -struct nouveau_barobj { - struct nouveau_object base; - struct nouveau_vma vma; +struct nvkm_barobj { + struct nvkm_object base; + struct nvkm_vma vma; void __iomem *iomem; }; static int -nouveau_barobj_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nvkm_barobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); - struct nouveau_bar *bar = nouveau_bar(device); - struct nouveau_mem *mem = data; - struct nouveau_barobj *barobj; + struct nvkm_device *device = nv_device(parent); + struct nvkm_bar *bar = nvkm_bar(device); + struct nvkm_mem *mem = data; + struct nvkm_barobj *barobj; int ret; - ret = nouveau_object_create(parent, engine, oclass, 0, &barobj); + ret = nvkm_object_create(parent, engine, oclass, 0, &barobj); *pobject = nv_object(barobj); if (ret) return ret; @@ -67,67 +64,65 @@ nouveau_barobj_ctor(struct nouveau_object *parent, } static void -nouveau_barobj_dtor(struct nouveau_object *object) +nvkm_barobj_dtor(struct nvkm_object *object) { - struct nouveau_bar *bar = nouveau_bar(object); - struct nouveau_barobj *barobj = (void *)object; + struct nvkm_bar *bar = nvkm_bar(object); + struct nvkm_barobj *barobj = (void *)object; if (barobj->vma.node) { if (barobj->iomem) iounmap(barobj->iomem); bar->unmap(bar, &barobj->vma); } - nouveau_object_destroy(&barobj->base); + nvkm_object_destroy(&barobj->base); } static u32 -nouveau_barobj_rd32(struct nouveau_object *object, u64 addr) +nvkm_barobj_rd32(struct nvkm_object *object, u64 addr) { - struct nouveau_barobj *barobj = (void *)object; + struct nvkm_barobj *barobj = (void *)object; return ioread32_native(barobj->iomem + addr); } static void -nouveau_barobj_wr32(struct nouveau_object *object, u64 addr, u32 data) +nvkm_barobj_wr32(struct nvkm_object *object, u64 addr, u32 data) { - struct nouveau_barobj *barobj = (void *)object; + struct nvkm_barobj *barobj = (void *)object; iowrite32_native(data, barobj->iomem + addr); } -static struct nouveau_oclass -nouveau_barobj_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nouveau_barobj_ctor, - .dtor = nouveau_barobj_dtor, - .init = nouveau_object_init, - .fini = nouveau_object_fini, - .rd32 = nouveau_barobj_rd32, - .wr32 = nouveau_barobj_wr32, +static struct nvkm_oclass +nvkm_barobj_oclass = { + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nvkm_barobj_ctor, + .dtor = nvkm_barobj_dtor, + .init = nvkm_object_init, + .fini = nvkm_object_fini, + .rd32 = nvkm_barobj_rd32, + .wr32 = nvkm_barobj_wr32, }, }; int -nouveau_bar_alloc(struct nouveau_bar *bar, struct nouveau_object *parent, - struct nouveau_mem *mem, struct nouveau_object **pobject) +nvkm_bar_alloc(struct nvkm_bar *bar, struct nvkm_object *parent, + struct nvkm_mem *mem, struct nvkm_object **pobject) { - struct nouveau_object *gpuobj; - int ret = nouveau_object_ctor(parent, &parent->engine->subdev.object, - &nouveau_barobj_oclass, - mem, 0, &gpuobj); + struct nvkm_object *gpuobj; + int ret = nvkm_object_ctor(parent, &parent->engine->subdev.object, + &nvkm_barobj_oclass, mem, 0, &gpuobj); if (ret == 0) *pobject = gpuobj; return ret; } int -nouveau_bar_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, int length, void **pobject) +nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - struct nouveau_bar *bar; + struct nvkm_bar *bar; int ret; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "BARCTL", - "bar", length, pobject); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL", + "bar", length, pobject); bar = *pobject; if (ret) return ret; @@ -136,14 +131,14 @@ nouveau_bar_create_(struct nouveau_object *parent, } void -nouveau_bar_destroy(struct nouveau_bar *bar) +nvkm_bar_destroy(struct nvkm_bar *bar) { - nouveau_subdev_destroy(&bar->base); + nvkm_subdev_destroy(&bar->base); } void -_nouveau_bar_dtor(struct nouveau_object *object) +_nvkm_bar_dtor(struct nvkm_object *object) { - struct nouveau_bar *bar = (void *)object; - nouveau_bar_destroy(bar); + struct nvkm_bar *bar = (void *)object; + nvkm_bar_destroy(bar); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c new file mode 100644 index 000000000000..4c6d238dd3da --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -0,0 +1,218 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include +#include +#include + +struct gf100_bar_priv_vm { + struct nvkm_gpuobj *mem; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; + +struct gf100_bar_priv { + struct nvkm_bar base; + spinlock_t lock; + struct gf100_bar_priv_vm bar[2]; +}; + +static int +gf100_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) +{ + struct gf100_bar_priv *priv = (void *)bar; + int ret; + + ret = nvkm_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma); + if (ret) + return ret; + + nvkm_vm_map(vma, mem); + return 0; +} + +static int +gf100_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) +{ + struct gf100_bar_priv *priv = (void *)bar; + int ret; + + ret = nvkm_vm_get(priv->bar[1].vm, mem->size << 12, + mem->page_shift, flags, vma); + if (ret) + return ret; + + nvkm_vm_map(vma, mem); + return 0; +} + +static void +gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma) +{ + nvkm_vm_unmap(vma); + nvkm_vm_put(vma); +} + +static int +gf100_bar_ctor_vm(struct gf100_bar_priv *priv, struct gf100_bar_priv_vm *bar_vm, + int bar_nr) +{ + struct nvkm_device *device = nv_device(&priv->base); + struct nvkm_vm *vm; + resource_size_t bar_len; + int ret; + + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, + &bar_vm->mem); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, + &bar_vm->pgd); + if (ret) + return ret; + + bar_len = nv_device_resource_len(device, bar_nr); + + ret = nvkm_vm_new(device, 0, bar_len, 0, &vm); + if (ret) + return ret; + + atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); + + /* + * Bootstrap page table lookup. + */ + if (bar_nr == 3) { + ret = nvkm_gpuobj_new(nv_object(priv), NULL, + (bar_len >> 12) * 8, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, + &vm->pgt[0].obj[0]); + vm->pgt[0].refcount[0] = 1; + if (ret) + return ret; + } + + ret = nvkm_vm_ref(vm, &bar_vm->vm, bar_vm->pgd); + nvkm_vm_ref(NULL, &vm, NULL); + if (ret) + return ret; + + nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr)); + nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr)); + nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1)); + nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1)); + return 0; +} + +int +gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_device *device = nv_device(parent); + struct gf100_bar_priv *priv; + bool has_bar3 = nv_device_resource_len(device, 3) != 0; + int ret; + + ret = nvkm_bar_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + /* BAR3 */ + if (has_bar3) { + ret = gf100_bar_ctor_vm(priv, &priv->bar[0], 3); + if (ret) + return ret; + } + + /* BAR1 */ + ret = gf100_bar_ctor_vm(priv, &priv->bar[1], 1); + if (ret) + return ret; + + if (has_bar3) { + priv->base.alloc = nvkm_bar_alloc; + priv->base.kmap = gf100_bar_kmap; + } + priv->base.umap = gf100_bar_umap; + priv->base.unmap = gf100_bar_unmap; + priv->base.flush = g84_bar_flush; + spin_lock_init(&priv->lock); + return 0; +} + +void +gf100_bar_dtor(struct nvkm_object *object) +{ + struct gf100_bar_priv *priv = (void *)object; + + nvkm_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd); + nvkm_gpuobj_ref(NULL, &priv->bar[1].pgd); + nvkm_gpuobj_ref(NULL, &priv->bar[1].mem); + + if (priv->bar[0].vm) { + nvkm_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]); + nvkm_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd); + } + nvkm_gpuobj_ref(NULL, &priv->bar[0].pgd); + nvkm_gpuobj_ref(NULL, &priv->bar[0].mem); + + nvkm_bar_destroy(&priv->base); +} + +int +gf100_bar_init(struct nvkm_object *object) +{ + struct gf100_bar_priv *priv = (void *)object; + int ret; + + ret = nvkm_bar_init(&priv->base); + if (ret) + return ret; + + nv_mask(priv, 0x000200, 0x00000100, 0x00000000); + nv_mask(priv, 0x000200, 0x00000100, 0x00000100); + + nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12); + if (priv->bar[0].mem) + nv_wr32(priv, 0x001714, + 0xc0000000 | priv->bar[0].mem->addr >> 12); + return 0; +} + +struct nvkm_oclass +gf100_bar_oclass = { + .handle = NV_SUBDEV(BAR, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_bar_ctor, + .dtor = gf100_bar_dtor, + .init = gf100_bar_init, + .fini = _nvkm_bar_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c index bf877af9d3bd..148f739a276e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c @@ -19,36 +19,32 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - -#include - #include "priv.h" int -gk20a_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk20a_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_bar *bar; + struct nvkm_bar *bar; int ret; - ret = nvc0_bar_ctor(parent, engine, oclass, data, size, pobject); + ret = gf100_bar_ctor(parent, engine, oclass, data, size, pobject); if (ret) return ret; - bar = (struct nouveau_bar *)*pobject; + bar = (struct nvkm_bar *)*pobject; bar->iomap_uncached = true; - return 0; } -struct nouveau_oclass +struct nvkm_oclass gk20a_bar_oclass = { .handle = NV_SUBDEV(BAR, 0xea), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk20a_bar_ctor, - .dtor = nvc0_bar_dtor, - .init = nvc0_bar_init, - .fini = _nouveau_bar_fini, + .dtor = gf100_bar_dtor, + .init = gf100_bar_init, + .fini = _nvkm_bar_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c index 6d0dd6a01e64..36c5c083c1e9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c @@ -21,66 +21,64 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include - -#include #include #include - -#include "priv.h" +#include struct nv50_bar_priv { - struct nouveau_bar base; + struct nvkm_bar base; spinlock_t lock; - struct nouveau_gpuobj *mem; - struct nouveau_gpuobj *pad; - struct nouveau_gpuobj *pgd; - struct nouveau_vm *bar1_vm; - struct nouveau_gpuobj *bar1; - struct nouveau_vm *bar3_vm; - struct nouveau_gpuobj *bar3; + struct nvkm_gpuobj *mem; + struct nvkm_gpuobj *pad; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *bar1_vm; + struct nvkm_gpuobj *bar1; + struct nvkm_vm *bar3_vm; + struct nvkm_gpuobj *bar3; }; static int -nv50_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem, - u32 flags, struct nouveau_vma *vma) +nv50_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) { struct nv50_bar_priv *priv = (void *)bar; int ret; - ret = nouveau_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma); + ret = nvkm_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma); if (ret) return ret; - nouveau_vm_map(vma, mem); + nvkm_vm_map(vma, mem); return 0; } static int -nv50_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem, - u32 flags, struct nouveau_vma *vma) +nv50_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) { struct nv50_bar_priv *priv = (void *)bar; int ret; - ret = nouveau_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma); + ret = nvkm_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma); if (ret) return ret; - nouveau_vm_map(vma, mem); + nvkm_vm_map(vma, mem); return 0; } static void -nv50_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma) +nv50_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma) { - nouveau_vm_unmap(vma); - nouveau_vm_put(vma); + nvkm_vm_unmap(vma); + nvkm_vm_put(vma); } static void -nv50_bar_flush(struct nouveau_bar *bar) +nv50_bar_flush(struct nvkm_bar *bar) { struct nv50_bar_priv *priv = (void *)bar; unsigned long flags; @@ -92,7 +90,7 @@ nv50_bar_flush(struct nouveau_bar *bar) } void -nv84_bar_flush(struct nouveau_bar *bar) +g84_bar_flush(struct nvkm_bar *bar) { struct nv50_bar_priv *priv = (void *)bar; unsigned long flags; @@ -104,36 +102,35 @@ nv84_bar_flush(struct nouveau_bar *bar) } static int -nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); - struct nouveau_object *heap; - struct nouveau_vm *vm; + struct nvkm_device *device = nv_device(parent); + struct nvkm_object *heap; + struct nvkm_vm *vm; struct nv50_bar_priv *priv; u64 start, limit; int ret; - ret = nouveau_bar_create(parent, engine, oclass, &priv); + ret = nvkm_bar_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0, - NVOBJ_FLAG_HEAP, &priv->mem); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x20000, 0, + NVOBJ_FLAG_HEAP, &priv->mem); heap = nv_object(priv->mem); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), heap, - (device->chipset == 0x50) ? 0x1400 : 0x0200, - 0, 0, &priv->pad); + ret = nvkm_gpuobj_new(nv_object(priv), heap, + (device->chipset == 0x50) ? 0x1400 : 0x0200, + 0, 0, &priv->pad); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), heap, 0x4000, 0, - 0, &priv->pgd); + ret = nvkm_gpuobj_new(nv_object(priv), heap, 0x4000, 0, 0, &priv->pgd); if (ret) return ret; @@ -141,25 +138,25 @@ nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, start = 0x0100000000ULL; limit = start + nv_device_resource_len(device, 3); - ret = nouveau_vm_new(device, start, limit, start, &vm); + ret = nvkm_vm_new(device, start, limit, start, &vm); if (ret) return ret; atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); - ret = nouveau_gpuobj_new(nv_object(priv), heap, - ((limit-- - start) >> 12) * 8, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]); + ret = nvkm_gpuobj_new(nv_object(priv), heap, + ((limit-- - start) >> 12) * 8, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]); vm->pgt[0].refcount[0] = 1; if (ret) return ret; - ret = nouveau_vm_ref(vm, &priv->bar3_vm, priv->pgd); - nouveau_vm_ref(NULL, &vm, NULL); + ret = nvkm_vm_ref(vm, &priv->bar3_vm, priv->pgd); + nvkm_vm_ref(NULL, &vm, NULL); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3); + ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3); if (ret) return ret; @@ -175,18 +172,18 @@ nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, start = 0x0000000000ULL; limit = start + nv_device_resource_len(device, 1); - ret = nouveau_vm_new(device, start, limit--, start, &vm); + ret = nvkm_vm_new(device, start, limit--, start, &vm); if (ret) return ret; atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); - ret = nouveau_vm_ref(vm, &priv->bar1_vm, priv->pgd); - nouveau_vm_ref(NULL, &vm, NULL); + ret = nvkm_vm_ref(vm, &priv->bar1_vm, priv->pgd); + nvkm_vm_ref(NULL, &vm, NULL); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1); + ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1); if (ret) return ret; @@ -198,42 +195,42 @@ nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_wo32(priv->bar1, 0x10, 0x00000000); nv_wo32(priv->bar1, 0x14, 0x00000000); - priv->base.alloc = nouveau_bar_alloc; + priv->base.alloc = nvkm_bar_alloc; priv->base.kmap = nv50_bar_kmap; priv->base.umap = nv50_bar_umap; priv->base.unmap = nv50_bar_unmap; if (device->chipset == 0x50) priv->base.flush = nv50_bar_flush; else - priv->base.flush = nv84_bar_flush; + priv->base.flush = g84_bar_flush; spin_lock_init(&priv->lock); return 0; } static void -nv50_bar_dtor(struct nouveau_object *object) +nv50_bar_dtor(struct nvkm_object *object) { struct nv50_bar_priv *priv = (void *)object; - nouveau_gpuobj_ref(NULL, &priv->bar1); - nouveau_vm_ref(NULL, &priv->bar1_vm, priv->pgd); - nouveau_gpuobj_ref(NULL, &priv->bar3); + nvkm_gpuobj_ref(NULL, &priv->bar1); + nvkm_vm_ref(NULL, &priv->bar1_vm, priv->pgd); + nvkm_gpuobj_ref(NULL, &priv->bar3); if (priv->bar3_vm) { - nouveau_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]); - nouveau_vm_ref(NULL, &priv->bar3_vm, priv->pgd); + nvkm_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]); + nvkm_vm_ref(NULL, &priv->bar3_vm, priv->pgd); } - nouveau_gpuobj_ref(NULL, &priv->pgd); - nouveau_gpuobj_ref(NULL, &priv->pad); - nouveau_gpuobj_ref(NULL, &priv->mem); - nouveau_bar_destroy(&priv->base); + nvkm_gpuobj_ref(NULL, &priv->pgd); + nvkm_gpuobj_ref(NULL, &priv->pad); + nvkm_gpuobj_ref(NULL, &priv->mem); + nvkm_bar_destroy(&priv->base); } static int -nv50_bar_init(struct nouveau_object *object) +nv50_bar_init(struct nvkm_object *object) { struct nv50_bar_priv *priv = (void *)object; int ret, i; - ret = nouveau_bar_init(&priv->base); + ret = nvkm_bar_init(&priv->base); if (ret) return ret; @@ -255,16 +252,16 @@ nv50_bar_init(struct nouveau_object *object) } static int -nv50_bar_fini(struct nouveau_object *object, bool suspend) +nv50_bar_fini(struct nvkm_object *object, bool suspend) { struct nv50_bar_priv *priv = (void *)object; - return nouveau_bar_fini(&priv->base, suspend); + return nvkm_bar_fini(&priv->base, suspend); } -struct nouveau_oclass +struct nvkm_oclass nv50_bar_oclass = { .handle = NV_SUBDEV(BAR, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_bar_ctor, .dtor = nv50_bar_dtor, .init = nv50_bar_init, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c deleted file mode 100644 index c7ac57ba8e35..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nvc0.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include - -#include -#include -#include - -#include "priv.h" - -struct nvc0_bar_priv_vm { - struct nouveau_gpuobj *mem; - struct nouveau_gpuobj *pgd; - struct nouveau_vm *vm; -}; - -struct nvc0_bar_priv { - struct nouveau_bar base; - spinlock_t lock; - struct nvc0_bar_priv_vm bar[2]; -}; - -static int -nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem, - u32 flags, struct nouveau_vma *vma) -{ - struct nvc0_bar_priv *priv = (void *)bar; - int ret; - - ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma); - if (ret) - return ret; - - nouveau_vm_map(vma, mem); - return 0; -} - -static int -nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem, - u32 flags, struct nouveau_vma *vma) -{ - struct nvc0_bar_priv *priv = (void *)bar; - int ret; - - ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12, - mem->page_shift, flags, vma); - if (ret) - return ret; - - nouveau_vm_map(vma, mem); - return 0; -} - -static void -nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma) -{ - nouveau_vm_unmap(vma); - nouveau_vm_put(vma); -} - -static int -nvc0_bar_init_vm(struct nvc0_bar_priv *priv, struct nvc0_bar_priv_vm *bar_vm, - int bar_nr) -{ - struct nouveau_device *device = nv_device(&priv->base); - struct nouveau_vm *vm; - resource_size_t bar_len; - int ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, - &bar_vm->mem); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, - &bar_vm->pgd); - if (ret) - return ret; - - bar_len = nv_device_resource_len(device, bar_nr); - - ret = nouveau_vm_new(device, 0, bar_len, 0, &vm); - if (ret) - return ret; - - atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); - - /* - * Bootstrap page table lookup. - */ - if (bar_nr == 3) { - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (bar_len >> 12) * 8, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, - &vm->pgt[0].obj[0]); - vm->pgt[0].refcount[0] = 1; - if (ret) - return ret; - } - - ret = nouveau_vm_ref(vm, &bar_vm->vm, bar_vm->pgd); - nouveau_vm_ref(NULL, &vm, NULL); - if (ret) - return ret; - - nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr)); - nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr)); - nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1)); - nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1)); - - return 0; -} - -int -nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_device *device = nv_device(parent); - struct nvc0_bar_priv *priv; - bool has_bar3 = nv_device_resource_len(device, 3) != 0; - int ret; - - ret = nouveau_bar_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - /* BAR3 */ - if (has_bar3) { - ret = nvc0_bar_init_vm(priv, &priv->bar[0], 3); - if (ret) - return ret; - } - - /* BAR1 */ - ret = nvc0_bar_init_vm(priv, &priv->bar[1], 1); - if (ret) - return ret; - - if (has_bar3) { - priv->base.alloc = nouveau_bar_alloc; - priv->base.kmap = nvc0_bar_kmap; - } - priv->base.umap = nvc0_bar_umap; - priv->base.unmap = nvc0_bar_unmap; - priv->base.flush = nv84_bar_flush; - spin_lock_init(&priv->lock); - return 0; -} - -void -nvc0_bar_dtor(struct nouveau_object *object) -{ - struct nvc0_bar_priv *priv = (void *)object; - - nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd); - nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd); - nouveau_gpuobj_ref(NULL, &priv->bar[1].mem); - - if (priv->bar[0].vm) { - nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]); - nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd); - } - nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd); - nouveau_gpuobj_ref(NULL, &priv->bar[0].mem); - - nouveau_bar_destroy(&priv->base); -} - -int -nvc0_bar_init(struct nouveau_object *object) -{ - struct nvc0_bar_priv *priv = (void *)object; - int ret; - - ret = nouveau_bar_init(&priv->base); - if (ret) - return ret; - - nv_mask(priv, 0x000200, 0x00000100, 0x00000000); - nv_mask(priv, 0x000200, 0x00000100, 0x00000100); - - nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12); - if (priv->bar[0].mem) - nv_wr32(priv, 0x001714, - 0xc0000000 | priv->bar[0].mem->addr >> 12); - return 0; -} - -struct nouveau_oclass -nvc0_bar_oclass = { - .handle = NV_SUBDEV(BAR, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_bar_ctor, - .dtor = nvc0_bar_dtor, - .init = nvc0_bar_init, - .fini = _nouveau_bar_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h index 3ee8b1476d00..aa85f61b48c2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h @@ -1,32 +1,30 @@ #ifndef __NVKM_BAR_PRIV_H__ #define __NVKM_BAR_PRIV_H__ - #include -#define nouveau_bar_create(p,e,o,d) \ - nouveau_bar_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_bar_init(p) \ - nouveau_subdev_init(&(p)->base) -#define nouveau_bar_fini(p,s) \ - nouveau_subdev_fini(&(p)->base, (s)) - -int nouveau_bar_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void nouveau_bar_destroy(struct nouveau_bar *); +#define nvkm_bar_create(p,e,o,d) \ + nvkm_bar_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_bar_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_bar_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) -void _nouveau_bar_dtor(struct nouveau_object *); -#define _nouveau_bar_init _nouveau_subdev_init -#define _nouveau_bar_fini _nouveau_subdev_fini +int nvkm_bar_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void nvkm_bar_destroy(struct nvkm_bar *); -int nouveau_bar_alloc(struct nouveau_bar *, struct nouveau_object *, - struct nouveau_mem *, struct nouveau_object **); +void _nvkm_bar_dtor(struct nvkm_object *); +#define _nvkm_bar_init _nvkm_subdev_init +#define _nvkm_bar_fini _nvkm_subdev_fini -void nv84_bar_flush(struct nouveau_bar *); +int nvkm_bar_alloc(struct nvkm_bar *, struct nvkm_object *, + struct nvkm_mem *, struct nvkm_object **); -int nvc0_bar_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nvc0_bar_dtor(struct nouveau_object *); -int nvc0_bar_init(struct nouveau_object *); +void g84_bar_flush(struct nvkm_bar *); +int gf100_bar_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void gf100_bar_dtor(struct nvkm_object *); +int gf100_bar_init(struct nvkm_object *); #endif