From: Paul Walmsley Date: Fri, 11 Mar 2011 05:43:05 +0000 (-0700) Subject: Merge remote branch 'remotes/origin/hwmod_a_2.6.39' into tmp-integration-2.6.39-20110... X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=2d403fe03070b541cc93cfa915f6e6c592cf231c;p=deliverable%2Flinux.git Merge remote branch 'remotes/origin/hwmod_a_2.6.39' into tmp-integration-2.6.39-20110310-024 Conflicts: arch/arm/mach-omap2/omap_hwmod_2430_data.c arch/arm/mach-omap2/omap_hwmod_3xxx_data.c arch/arm/plat-omap/include/plat/omap_hwmod.h --- 2d403fe03070b541cc93cfa915f6e6c592cf231c diff --cc arch/arm/mach-omap2/omap_hwmod_2430_data.c index 490789a6bed0,115eed51b521..0fdf2cabfb12 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@@ -1077,1234 -662,47 +1077,1236 @@@ static struct omap_hwmod_ocp_if omap243 .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* gpio dev_attr */ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = false, +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), ++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap2430_wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable +}; + +/* wd_timer2 */ +static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { + &omap2430_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap2430_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap2430_wd_timer_hwmod_class, + .main_clk = "mpu_wdt_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, + }, + }, + .slaves = omap2430_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* UART */ + +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), ++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +/* UART1 */ + +static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { + { .irq = INT_24XX_UART1_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { + &omap2_l4_core__uart1, +}; + +static struct omap_hwmod omap2430_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = uart1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), + .sdma_reqs = uart1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, + }, + }, + .slaves = omap2430_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* UART2 */ + +static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { + { .irq = INT_24XX_UART2_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { + &omap2_l4_core__uart2, +}; + +static struct omap_hwmod omap2430_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = uart2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), + .sdma_reqs = uart2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, + }, + }, + .slaves = omap2430_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* UART3 */ + +static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { + { .irq = INT_24XX_UART3_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { + &omap2_l4_core__uart3, +}; + +static struct omap_hwmod omap2430_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = uart3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), + .sdma_reqs = uart3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP24XX_EN_UART3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, + }, + }, + .slaves = omap2430_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* + * 'dss' class + * display sub-system + */ + +static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_dss_hwmod_class = { + .name = "dss", + .sysc = &omap2430_dss_sysc, +}; + +/* dss */ +static struct omap_hwmod_irq_info omap2430_dss_irqs[] = { + { .irq = 25 }, +}; +static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = { + { .name = "dispc", .dma_req = 5 }, +}; + +/* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { + &omap2430_dss__l3, +}; + +static struct omap_hwmod_addr_space omap2430_dss_addrs[] = { + { + .pa_start = 0x48050000, + .pa_end = 0x480503FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2430_dss_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { + &omap2430_l4_core__dss, +}; + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + { .role = "tv_clk", .clk = "dss_54m_fck" }, + { .role = "sys_clk", .clk = "dss2_fck" }, +}; + +static struct omap_hwmod omap2430_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2430_dss_hwmod_class, + .main_clk = "dss1_fck", /* instead of dss_fck */ + .mpu_irqs = omap2430_dss_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dss_irqs), + .sdma_reqs = omap2430_dss_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap2430_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), + .masters = omap2430_dss_masters, + .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap2430_dispc_sysc, +}; + +static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = { + { + .pa_start = 0x48050400, + .pa_end = 0x480507FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2430_dss_dispc_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { + &omap2430_l4_core__dss_dispc, +}; + +static struct omap_hwmod omap2430_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap2430_dispc_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .slaves = omap2430_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'rfbi' class + * remote frame buffer interface + */ + +static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_rfbi_hwmod_class = { + .name = "rfbi", + .sysc = &omap2430_rfbi_sysc, +}; + +static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = { + { + .pa_start = 0x48050800, + .pa_end = 0x48050BFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2430_dss_rfbi_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { + &omap2430_l4_core__dss_rfbi, +}; + +static struct omap_hwmod omap2430_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2430_rfbi_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .slaves = omap2430_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'venc' class + * video encoder + */ + +static struct omap_hwmod_class omap2430_venc_hwmod_class = { + .name = "venc", +}; + +/* dss_venc */ +static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = { + { + .pa_start = 0x48050C00, + .pa_end = 0x48050FFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_venc_hwmod, + .clk = "dss_54m_fck", + .addr = omap2430_dss_venc_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs), + .flags = OCPIF_SWSUP_IDLE, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { + &omap2430_l4_core__dss_venc, +}; + +static struct omap_hwmod omap2430_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap2430_venc_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .slaves = omap2430_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, +}; + +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | ++ SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +/* I2C1 */ + +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = INT_24XX_I2C1_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { + &omap2430_l4_core__i2c1, +}; + +static struct omap_hwmod omap2430_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = i2c1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), + .sdma_reqs = i2c1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), + .main_clk = "i2chs1_fck", + .prcm = { + .omap2 = { + /* + * NOTE: The CM_FCLKEN* and CM_ICLKEN* for + * I2CHS IP's do not follow the usual pattern. + * prcm_reg_id alone cannot be used to program + * the iclk and fclk. Needs to be handled using + * additonal flags when clk handling is moved + * to hwmod framework. + */ + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, + }, + }, + .slaves = omap2430_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* I2C2 */ + +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = INT_24XX_I2C2_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { + &omap2430_l4_core__i2c2, +}; + +static struct omap_hwmod omap2430_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = i2c2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), + .sdma_reqs = i2c2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), + .main_clk = "i2chs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, + }, + }, + .slaves = omap2430_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { + { + .pa_start = 0x4900C000, + .pa_end = 0x4900C1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio1_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio2 */ +static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { + { + .pa_start = 0x4900E000, + .pa_end = 0x4900E1ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio2_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio3 */ +static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { + { + .pa_start = 0x49010000, + .pa_end = 0x490101ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio3_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio3_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio4 */ +static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { + { + .pa_start = 0x49012000, + .pa_end = 0x490121ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_gpio4_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio4_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> gpio5 */ +static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { + { + .pa_start = 0x480B6000, + .pa_end = 0x480B61ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_gpio5_hwmod, + .clk = "gpio5_ick", + .addr = omap2430_gpio5_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpio dev_attr */ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = false, +}; + +static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | ++ SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +/* + * 'gpio' class + * general purpose io module + */ +static struct omap_hwmod_class omap243x_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap243x_gpio_sysc, + .rev = 0, +}; + +/* gpio1 */ +static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { + { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { + &omap2430_l4_wkup__gpio1, +}; + +static struct omap_hwmod omap2430_gpio1_hwmod = { + .name = "gpio1", + .mpu_irqs = omap243x_gpio1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* gpio2 */ +static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { + { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { + &omap2430_l4_wkup__gpio2, +}; + +static struct omap_hwmod omap2430_gpio2_hwmod = { + .name = "gpio2", + .mpu_irqs = omap243x_gpio2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* gpio3 */ +static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { + { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { + &omap2430_l4_wkup__gpio3, +}; + +static struct omap_hwmod omap2430_gpio3_hwmod = { + .name = "gpio3", + .mpu_irqs = omap243x_gpio3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* gpio4 */ +static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { + { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { + &omap2430_l4_wkup__gpio4, +}; + +static struct omap_hwmod omap2430_gpio4_hwmod = { + .name = "gpio4", + .mpu_irqs = omap243x_gpio4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .slaves = omap2430_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* gpio5 */ +static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { + { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { + &omap2430_l4_core__gpio5, +}; + +static struct omap_hwmod omap2430_gpio5_hwmod = { + .name = "gpio5", + .mpu_irqs = omap243x_gpio5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), + .main_clk = "gpio5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_GPIO5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, + }, + }, + .slaves = omap2430_gpio5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), + .class = &omap243x_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* dma_system */ +static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | + SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | - SYSC_HAS_AUTOIDLE), ++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_dma_hwmod_class = { + .name = "dma", + .sysc = &omap2430_dma_sysc, +}; + +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, +}; + +static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { + { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ + { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ + { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ + { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ +}; + +static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x4a0560ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { + .master = &omap2430_dma_system_hwmod, + .slave = &omap2430_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { + &omap2430_dma_system__l3, +}; + +/* l4_core -> dma_system */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dma_system_hwmod, + .clk = "sdma_ick", + .addr = omap2430_dma_system_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { + &omap2430_l4_core__dma_system, +}; + +static struct omap_hwmod omap2430_dma_system_hwmod = { + .name = "dma", + .class = &omap2430_dma_hwmod_class, + .mpu_irqs = omap2430_dma_system_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), + .main_clk = "core_l3_ck", + .slaves = omap2430_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), + .masters = omap2430_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), + .dev_attr = &dma_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'mailbox' class + * mailbox module allowing communication between the on-chip processors + * using a queued mailbox-interrupt mechanism. + */ + +static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &omap2430_mailbox_sysc, +}; + +/* mailbox */ +static struct omap_hwmod omap2430_mailbox_hwmod; +static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { + { .irq = 26 }, +}; + +static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = { + { + .pa_start = 0x48094000, + .pa_end = 0x480941ff, + .flags = ADDR_TYPE_RT, + }, +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mailbox_hwmod, + .addr = omap2430_mailbox_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mailbox slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = { + &omap2430_l4_core__mailbox, +}; + +static struct omap_hwmod omap2430_mailbox_hwmod = { + .name = "mailbox", + .class = &omap2430_mailbox_hwmod_class, + .mpu_irqs = omap2430_mailbox_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs), + .main_clk = "mailboxes_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, + }, + }, + .slaves = omap2430_mailbox_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* + * 'mcspi' class + * multichannel serial port interface (mcspi) / master/slave synchronous serial + * bus + */ + +static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_mcspi_class = { + .name = "mcspi", + .sysc = &omap2430_mcspi_sysc, + .rev = OMAP2_MCSPI_REV, +}; + +/* mcspi1 */ +static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = { + { .irq = 65 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = { + { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ + { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ + { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ + { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ + { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ + { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ + { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ + { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { + &omap2430_l4_core__mcspi1, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +static struct omap_hwmod omap2430_mcspi1_hwmod = { + .name = "mcspi1_hwmod", + .mpu_irqs = omap2430_mcspi1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs), + .sdma_reqs = omap2430_mcspi1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs), + .main_clk = "mcspi1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, + }, + }, + .slaves = omap2430_mcspi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), + .class = &omap2430_mcspi_class, + .dev_attr = &omap_mcspi1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcspi2 */ +static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = { + { .irq = 66 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = { + { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ + { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ + { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ + { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { + &omap2430_l4_core__mcspi2, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap2430_mcspi2_hwmod = { + .name = "mcspi2_hwmod", + .mpu_irqs = omap2430_mcspi2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs), + .sdma_reqs = omap2430_mcspi2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs), + .main_clk = "mcspi2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, + }, + }, + .slaves = omap2430_mcspi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), + .class = &omap2430_mcspi_class, + .dev_attr = &omap_mcspi2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcspi3 */ +static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { + { .irq = 91 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { + { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ + { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ + { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ + { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { + &omap2430_l4_core__mcspi3, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap2430_mcspi3_hwmod = { + .name = "mcspi3_hwmod", + .mpu_irqs = omap2430_mcspi3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs), + .sdma_reqs = omap2430_mcspi3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs), + .main_clk = "mcspi3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MCSPI3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, + }, + }, + .slaves = omap2430_mcspi3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), + .class = &omap2430_mcspi_class, + .dev_attr = &omap_mcspi3_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* + * usbhsotg + */ +static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class usbotg_class = { + .name = "usbotg", + .sysc = &omap2430_usbhsotg_sysc, +}; + +/* usb_otg_hs */ +static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { + + { .name = "mc", .irq = 92 }, + { .name = "dma", .irq = 93 }, +}; + +static struct omap_hwmod omap2430_usbhsotg_hwmod = { + .name = "usb_otg_hs", + .mpu_irqs = omap2430_usbhsotg_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs), + .main_clk = "usbhs_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_USBHS_MASK, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, + }, + }, + .masters = omap2430_usbhsotg_masters, + .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), + .slaves = omap2430_usbhsotg_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), + .class = &usbotg_class, + /* + * Erratum ID: i479 idle_req / idle_ack mechanism potentially + * broken when autoidle is enabled + * workaround is to disable the autoidle bit at module level. + */ + .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE + | HWMOD_SWSUP_MSTANDBY, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { + .rev_offs = 0x007C, + .sysc_offs = 0x008C, + .sysc_flags = (SYSC_HAS_SOFTRESET), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap2430_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE2, +}; + +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, + { .name = "ovr", .irq = 61 }, + { .name = "common", .irq = 64 }, }; -static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, +static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = { + { .name = "rx", .dma_req = 32 }, + { .name = "tx", .dma_req = 31 }, }; -/* - * 'gpio' class - * general purpose io module - */ -static struct omap_hwmod_class omap243x_gpio_hwmod_class = { - .name = "gpio", - .sysc = &omap243x_gpio_sysc, - .rev = 0, +static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48074000, + .pa_end = 0x480740ff, + .flags = ADDR_TYPE_RT + }, }; -/* gpio1 */ -static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { - { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap2430_mcbsp1_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { - &omap2430_l4_wkup__gpio1, +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = { + &omap2430_l4_core__mcbsp1, }; -static struct omap_hwmod omap2430_gpio1_hwmod = { - .name = "gpio1", - .mpu_irqs = omap243x_gpio1_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), - .main_clk = "gpios_fck", +static struct omap_hwmod omap2430_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs), + .sdma_reqs = omap2430_mcbsp1_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs), + .main_clk = "mcbsp1_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, diff --cc arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 2e275cbcd654,acf0d54024ab..17b4fb8c3479 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@@ -1184,1776 -893,54 +1184,1779 @@@ static struct omap_hwmod_ocp_if omap3xx .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* - * 'gpio' class - * general purpose io module - */ +/* timer12 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { + &omap3xxx_l4_core__timer12, +}; -static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | +/* timer12 hwmod */ +static struct omap_hwmod omap3xxx_timer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap3xxx_timer12_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs), + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT12_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, + }, + }, + .slaves = omap3xxx_timer12_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { + { + .pa_start = 0x48314000, + .pa_end = 0x4831407f, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_wd_timer2_hwmod, + .clk = "wdt2_ick", + .addr = omap3xxx_wd_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), ++ SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSS_HAS_RESET_STATUS), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), ++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap3xxx_wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable +}; + +/* wd_timer2 */ +static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { + &omap3xxx_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap3xxx_wd_timer_hwmod_class, + .main_clk = "wdt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_WDT2_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, + }, + }, + .slaves = omap3xxx_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + /* + * XXX: Use software supervised mode, HW supervised smartidle seems to + * block CORE power domain idle transitions. Maybe a HW bug in wdt2? + */ + .flags = HWMOD_SWSUP_SIDLE, +}; + +/* UART common */ + +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), ++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +/* UART1 */ + +static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { + { .irq = INT_24XX_UART1_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, + { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { + &omap3_l4_core__uart1, +}; + +static struct omap_hwmod omap3xxx_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = uart1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), + .sdma_reqs = uart1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, + }, + }, + .slaves = omap3xxx_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART2 */ + +static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { + { .irq = INT_24XX_UART2_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, + { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { + &omap3_l4_core__uart2, +}; + +static struct omap_hwmod omap3xxx_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = uart2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), + .sdma_reqs = uart2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, + }, + }, + .slaves = omap3xxx_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART3 */ + +static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { + { .irq = INT_24XX_UART3_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, + { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { + &omap3_l4_per__uart3, +}; + +static struct omap_hwmod omap3xxx_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = uart3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), + .sdma_reqs = uart3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430_PER_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, + }, + }, + .slaves = omap3xxx_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART4 */ + +static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { + { .irq = INT_36XX_UART4_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, + { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { + &omap3_l4_per__uart4, +}; + +static struct omap_hwmod omap3xxx_uart4_hwmod = { + .name = "uart4", + .mpu_irqs = uart4_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), + .sdma_reqs = uart4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), + .main_clk = "uart4_fck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430_PER_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3630_EN_UART4_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, + }, + }, + .slaves = omap3xxx_uart4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +/* + * 'dss' class + * display sub-system + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_dss_hwmod_class = { + .name = "dss", + .sysc = &omap3xxx_dss_sysc, +}; + +/* dss */ +static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = { + { .irq = 25 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { + { .name = "dispc", .dma_req = 5 }, + { .name = "dsi1", .dma_req = 74 }, +}; + +/* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { + &omap3xxx_dss__l3, +}; + +static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = { + { + .pa_start = 0x48050000, + .pa_end = 0x480503FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3430es1_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { + &omap3430es1_l4_core__dss, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { + &omap3xxx_l4_core__dss, +}; + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + { .role = "tv_clk", .clk = "dss_tv_fck" }, + { .role = "dssclk", .clk = "dss_96m_fck" }, + { .role = "sys_clk", .clk = "dss2_alwon_fck" }, +}; + +static struct omap_hwmod omap3430es1_dss_core_hwmod = { + .name = "dss_core", + .class = &omap3xxx_dss_hwmod_class, + .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ + .mpu_irqs = omap3xxx_dss_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), + .sdma_reqs = omap3xxx_dss_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), + + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap3430es1_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), + .masters = omap3xxx_dss_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), + .flags = HWMOD_NO_IDLEST, +}; + +static struct omap_hwmod omap3xxx_dss_core_hwmod = { + .name = "dss_core", + .class = &omap3xxx_dss_hwmod_class, + .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ + .mpu_irqs = omap3xxx_dss_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), + .sdma_reqs = omap3xxx_dss_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), + + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap3xxx_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), + .masters = omap3xxx_dss_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 | + CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), +}; + +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap3xxx_dispc_sysc, +}; + +static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = { + { + .pa_start = 0x48050400, + .pa_end = 0x480507FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_dispc_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { + &omap3xxx_l4_core__dss_dispc, +}; + +static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap3xxx_dispc_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'dsi' class + * display serial interface controller + */ + +static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { + .name = "dsi", +}; + +/* dss_dsi1 */ +static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { + { + .pa_start = 0x4804FC00, + .pa_end = 0x4804FFFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dsi1_hwmod, + .addr = omap3xxx_dss_dsi1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dsi1 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { + &omap3xxx_l4_core__dss_dsi1, +}; + +static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { + .name = "dss_dsi1", + .class = &omap3xxx_dsi_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_dsi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'rfbi' class + * remote frame buffer interface + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = { + .name = "rfbi", + .sysc = &omap3xxx_rfbi_sysc, +}; + +static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = { + { + .pa_start = 0x48050800, + .pa_end = 0x48050BFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_rfbi_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { + &omap3xxx_l4_core__dss_rfbi, +}; + +static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap3xxx_rfbi_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'venc' class + * video encoder + */ + +static struct omap_hwmod_class omap3xxx_venc_hwmod_class = { + .name = "venc", +}; + +/* dss_venc */ +static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = { + { + .pa_start = 0x48050C00, + .pa_end = 0x48050FFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_venc_hwmod, + .clk = "dss_tv_fck", + .addr = omap3xxx_dss_venc_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .flags = OCPIF_SWSUP_IDLE, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { + &omap3xxx_l4_core__dss_venc, +}; + +static struct omap_hwmod omap3xxx_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap3xxx_venc_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + +/* I2C1 */ + +static struct omap_i2c_dev_attr i2c1_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = INT_24XX_I2C1_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { + &omap3_l4_core__i2c1, +}; + +static struct omap_hwmod omap3xxx_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = i2c1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), + .sdma_reqs = i2c1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), + .main_clk = "i2c1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_I2C1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, + }, + }, + .slaves = omap3xxx_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* I2C2 */ + +static struct omap_i2c_dev_attr i2c2_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = INT_24XX_I2C2_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { + &omap3_l4_core__i2c2, +}; + +static struct omap_hwmod omap3xxx_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = i2c2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), + .sdma_reqs = i2c2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), + .main_clk = "i2c2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_I2C2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, + }, + }, + .slaves = omap3xxx_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* I2C3 */ + +static struct omap_i2c_dev_attr i2c3_dev_attr = { + .fifo_depth = 64, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { + { .irq = INT_34XX_I2C3_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, + { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { + &omap3_l4_core__i2c3, +}; + +static struct omap_hwmod omap3xxx_i2c3_hwmod = { + .name = "i2c3", + .mpu_irqs = i2c3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs), + .sdma_reqs = i2c3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs), + .main_clk = "i2c3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_I2C3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, + }, + }, + .slaves = omap3xxx_i2c3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), + .class = &i2c_class, + .dev_attr = &i2c3_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { + { + .pa_start = 0x48310000, + .pa_end = 0x483101ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_gpio1_hwmod, + .addr = omap3xxx_gpio1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio2 */ +static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { + { + .pa_start = 0x49050000, + .pa_end = 0x490501ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio2_hwmod, + .addr = omap3xxx_gpio2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio3 */ +static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { + { + .pa_start = 0x49052000, + .pa_end = 0x490521ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio3_hwmod, + .addr = omap3xxx_gpio3_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio4 */ +static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { + { + .pa_start = 0x49054000, + .pa_end = 0x490541ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio4_hwmod, + .addr = omap3xxx_gpio4_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio5 */ +static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { + { + .pa_start = 0x49056000, + .pa_end = 0x490561ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio5_hwmod, + .addr = omap3xxx_gpio5_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio6 */ +static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { + { + .pa_start = 0x49058000, + .pa_end = 0x490581ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio6_hwmod, + .addr = omap3xxx_gpio6_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* + * 'gpio' class + * general purpose io module + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), ++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | ++ SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap3xxx_gpio_sysc, + .rev = 1, +}; + +/* gpio_dev_attr*/ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, +}; + +/* gpio1 */ +static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = { + { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */ +}; + +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { + &omap3xxx_l4_wkup__gpio1, +}; + +static struct omap_hwmod omap3xxx_gpio1_hwmod = { + .name = "gpio1", + .mpu_irqs = omap3xxx_gpio1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs), + .main_clk = "gpio1_ick", + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, + }, + }, + .slaves = omap3xxx_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* gpio2 */ +static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = { + { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */ +}; + +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { + &omap3xxx_l4_per__gpio2, +}; + +static struct omap_hwmod omap3xxx_gpio2_hwmod = { + .name = "gpio2", + .mpu_irqs = omap3xxx_gpio2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs), + .main_clk = "gpio2_ick", + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, + }, + }, + .slaves = omap3xxx_gpio2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* gpio3 */ +static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = { + { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */ +}; + +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { + &omap3xxx_l4_per__gpio3, +}; + +static struct omap_hwmod omap3xxx_gpio3_hwmod = { + .name = "gpio3", + .mpu_irqs = omap3xxx_gpio3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs), + .main_clk = "gpio3_ick", + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, + }, + }, + .slaves = omap3xxx_gpio3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* gpio4 */ +static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = { + { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */ +}; + +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { + { .role = "dbclk", .clk = "gpio4_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { + &omap3xxx_l4_per__gpio4, +}; + +static struct omap_hwmod omap3xxx_gpio4_hwmod = { + .name = "gpio4", + .mpu_irqs = omap3xxx_gpio4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs), + .main_clk = "gpio4_ick", + .opt_clks = gpio4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, + }, + }, + .slaves = omap3xxx_gpio4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* gpio5 */ +static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { + { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ +}; + +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { + { .role = "dbclk", .clk = "gpio5_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { + &omap3xxx_l4_per__gpio5, +}; + +static struct omap_hwmod omap3xxx_gpio5_hwmod = { + .name = "gpio5", + .mpu_irqs = omap3xxx_gpio5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs), + .main_clk = "gpio5_ick", + .opt_clks = gpio5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO5_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, + }, + }, + .slaves = omap3xxx_gpio5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* gpio6 */ +static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { + { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ +}; + +static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { + { .role = "dbclk", .clk = "gpio6_dbck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { + &omap3xxx_l4_per__gpio6, +}; + +static struct omap_hwmod omap3xxx_gpio6_hwmod = { + .name = "gpio6", + .mpu_irqs = omap3xxx_gpio6_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs), + .main_clk = "gpio6_ick", + .opt_clks = gpio6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPIO6_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, + }, + }, + .slaves = omap3xxx_gpio6_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), + .class = &omap3xxx_gpio_hwmod_class, + .dev_attr = &gpio_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { + .master = &omap3xxx_dma_system_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, +}; + +static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), ++ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | ++ SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { + .name = "dma", + .sysc = &omap3xxx_dma_sysc, +}; + +/* dma_system */ +static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = { + { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ + { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ + { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ + { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ +}; + +static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x4a0560ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* dma_system master ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { + &omap3xxx_dma_system__l3, +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dma_system_hwmod, + .clk = "core_l4_ick", + .addr = omap3xxx_dma_system_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { + &omap3xxx_l4_core__dma_system, +}; + +static struct omap_hwmod omap3xxx_dma_system_hwmod = { + .name = "dma", + .class = &omap3xxx_dma_hwmod_class, + .mpu_irqs = omap3xxx_dma_system_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs), + .main_clk = "core_l3_ick", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_ST_SDMA_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, + }, + }, + .slaves = omap3xxx_dma_system_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), + .masters = omap3xxx_dma_system_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), + .dev_attr = &dma_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { + .sysc_offs = 0x008c, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, + .clockact = 0x2, +}; + +static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap3xxx_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE3, +}; + +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { + { .name = "irq", .irq = 16 }, + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = { + { .name = "rx", .dma_req = 32 }, + { .name = "tx", .dma_req = 31 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48074000, + .pa_end = 0x480740ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap3xxx_mcbsp1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = { + &omap3xxx_l4_core__mcbsp1, +}; + +static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs), + .sdma_reqs = omap3xxx_mcbsp1_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs), + .main_clk = "mcbsp1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { + { .name = "irq", .irq = 17 }, + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = { + { .name = "rx", .dma_req = 34 }, + { .name = "tx", .dma_req = 33 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { + &omap3xxx_l4_per__mcbsp2, +}; + +static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { + .sidetone = "mcbsp2_sidetone", +}; + +static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs), + .sdma_reqs = omap3xxx_mcbsp2_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs), + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), + .dev_attr = &omap34xx_mcbsp2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp3 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { + { .name = "irq", .irq = 22 }, + { .name = "tx", .irq = 89 }, + { .name = "rx", .irq = 90 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = { + { .name = "rx", .dma_req = 18 }, + { .name = "tx", .dma_req = 17 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp3 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { + &omap3xxx_l4_per__mcbsp3, +}; + +static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { + .sidetone = "mcbsp3_sidetone", +}; + +static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs), + .sdma_reqs = omap3xxx_mcbsp3_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs), + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), + .dev_attr = &omap34xx_mcbsp3_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp4 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { + { .name = "irq", .irq = 23 }, + { .name = "tx", .irq = 54 }, + { .name = "rx", .irq = 55 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { + { .name = "rx", .dma_req = 20 }, + { .name = "tx", .dma_req = 19 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap3xxx_mcbsp4_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp4 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = { + &omap3xxx_l4_per__mcbsp4, +}; + +static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { + .name = "mcbsp4", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs), + .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs), + .main_clk = "mcbsp4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp5 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { + { .name = "irq", .irq = 27 }, + { .name = "tx", .irq = 81 }, + { .name = "rx", .irq = 82 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { + { .name = "rx", .dma_req = 22 }, + { .name = "tx", .dma_req = 21 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap3xxx_mcbsp5_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp5 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = { + &omap3xxx_l4_core__mcbsp5, +}; + +static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { + .name = "mcbsp5", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs), + .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs), + .main_clk = "mcbsp5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; +/* 'mcbsp sidetone' class */ + +static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { + .sysc_offs = 0x0010, + .sysc_flags = SYSC_HAS_AUTOIDLE, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { + .name = "mcbsp_sidetone", + .sysc = &omap3xxx_mcbsp_sidetone_sysc, +}; + +/* mcbsp2_sidetone */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { + { .name = "irq", .irq = 4 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x49028000, + .pa_end = 0x490280ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp2_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_sidetone_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_sidetone_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs), + .user = OCP_USER_MPU, +}; + +/* mcbsp2_sidetone slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = { + &omap3xxx_l4_per__mcbsp2_sidetone, +}; + +static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { + .name = "mcbsp2_sidetone", + .class = &omap3xxx_mcbsp_sidetone_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs), + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp2_sidetone_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp3_sidetone */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { + { .name = "irq", .irq = 5 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x4902A000, + .pa_end = 0x4902A0ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp3_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_sidetone_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_sidetone_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs), + .user = OCP_USER_MPU, +}; + +/* mcbsp3_sidetone slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = { + &omap3xxx_l4_per__mcbsp3_sidetone, +}; + +static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { + .name = "mcbsp3_sidetone", + .class = &omap3xxx_mcbsp_sidetone_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs), + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp3_sidetone_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + + +/* SR common */ +static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { + .clkact_shift = 20, +}; + +static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { + .sysc_offs = 0x24, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), + .clockact = CLOCKACT_TEST_ICLK, + .sysc_fields = &omap34xx_sr_sysc_fields, +}; + +static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { + .name = "smartreflex", + .sysc = &omap34xx_sr_sysc, + .rev = 1, +}; + +static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { + .sidle_shift = 24, + .enwkup_shift = 26 +}; + +static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { + .sysc_offs = 0x38, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_NO_CACHE), + .sysc_fields = &omap36xx_sr_sysc_fields, }; -static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { - .name = "gpio", - .sysc = &omap3xxx_gpio_sysc, - .rev = 1, +static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { + .name = "smartreflex", + .sysc = &omap36xx_sr_sysc, + .rev = 2, }; -/* gpio_dev_attr*/ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = true, +/* SR1 */ +static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { + &omap3_l4_core__sr1, }; -/* gpio1 */ -static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = { - { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */ +static struct omap_hwmod omap34xx_sr1_hwmod = { + .name = "sr1_hwmod", + .class = &omap34xx_smartreflex_hwmod_class, + .main_clk = "sr1_fck", + .vdd_name = "mpu", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, + }, + }, + .slaves = omap3_sr1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | + CHIP_IS_OMAP3430ES3_0 | + CHIP_IS_OMAP3430ES3_1), + .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; -static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { - { .role = "dbclk", .clk = "gpio1_dbck", }, +static struct omap_hwmod omap36xx_sr1_hwmod = { + .name = "sr1_hwmod", + .class = &omap36xx_smartreflex_hwmod_class, + .main_clk = "sr1_fck", + .vdd_name = "mpu", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SR1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, + }, + }, + .slaves = omap3_sr1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { - &omap3xxx_l4_wkup__gpio1, +/* SR2 */ +static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { + &omap3_l4_core__sr2, }; -static struct omap_hwmod omap3xxx_gpio1_hwmod = { - .name = "gpio1", - .mpu_irqs = omap3xxx_gpio1_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs), - .main_clk = "gpio1_ick", - .opt_clks = gpio1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), +static struct omap_hwmod omap34xx_sr2_hwmod = { + .name = "sr2_hwmod", + .class = &omap34xx_smartreflex_hwmod_class, + .main_clk = "sr2_fck", + .vdd_name = "core", .prcm = { .omap2 = { .prcm_reg_id = 1, diff --cc arch/arm/plat-omap/include/plat/omap_hwmod.h index 8a1368fbbbd3,78f1cc88ff06..fca0cbce4659 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@@ -373,11 -372,9 +375,11 @@@ struct omap_hwmod_omap4_prcm * of standby, rather than relying on module smart-standby * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for * SDRAM controller, etc. XXX probably belongs outside the main hwmod file + * XXX Should be HWMOD_SETUP_NO_RESET * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM * controller, etc. XXX probably belongs outside the main hwmod file + * XXX Should be HWMOD_SETUP_NO_IDLE - * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) + * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) * when module is enabled, rather than the default, which is to * enable autoidle * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup