From: Soren Brinkmann <soren.brinkmann@xilinx.com>
Date: Wed, 31 Jul 2013 23:24:59 +0000 (-0700)
Subject: arm: zynq: dt: Set correct L2 ram latencies
X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=39c41df9c1950fba0ee6a4e7a63be281e89fe437;p=deliverable%2Flinux.git

arm: zynq: dt: Set correct L2 ram latencies

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 6f54a64850eb..e32b92b949d2 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -41,8 +41,8 @@
 		L2: cache-controller {
 			compatible = "arm,pl310-cache";
 			reg = <0xF8F02000 0x1000>;
-			arm,data-latency = <2 3 2>;
-			arm,tag-latency = <2 3 2>;
+			arm,data-latency = <3 2 2>;
+			arm,tag-latency = <2 2 2>;
 			cache-unified;
 			cache-level = <2>;
 		};