From: Jan Beulich Date: Fri, 3 Jan 2020 09:14:16 +0000 (+0100) Subject: Arm64: correct {su,us}dot SIMD encodings X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=567dfba2bed4bce68a13b0c8963dec9605dea6c8;p=deliverable%2Fbinutils-gdb.git Arm64: correct {su,us}dot SIMD encodings According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 8a6470f4c6..4a8bb549b3 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2020-01-03 Jan Beulich + + * testsuite/gas/aarch64/i8mm.s: Add 128-bit form tests for + by-element usdot. Add 64-bit form tests for by-element sudot. + * testsuite/gas/aarch64/i8mm.d: Adjust expectations. + 2020-01-03 Jan Beulich * testsuite/gas/aarch64/f64mm.s: Drop 'i' from uzip. diff --git a/gas/testsuite/gas/aarch64/i8mm.d b/gas/testsuite/gas/aarch64/i8mm.d index 5d667f56c9..04cd1376ab 100644 --- a/gas/testsuite/gas/aarch64/i8mm.d +++ b/gas/testsuite/gas/aarch64/i8mm.d @@ -29,15 +29,23 @@ Disassembly of section \.text: *[0-9a-f]+: 6e80a400 ummla v0\.4s, v0\.16b, v0\.16b *[0-9a-f]+: 4e80ac00 usmmla v0\.4s, v0\.16b, v0\.16b *[0-9a-f]+: 4e9baeb1 usmmla v17\.4s, v21\.16b, v27\.16b - *[0-9a-f]+: 4e9b9eb1 usdot v17\.2s, v21\.8b, v27\.8b - *[0-9a-f]+: 4e809c00 usdot v0\.2s, v0\.8b, v0\.8b - *[0-9a-f]+: 4e9b9eb1 usdot v17\.2s, v21\.8b, v27\.8b - *[0-9a-f]+: 4e809c00 usdot v0\.2s, v0\.8b, v0\.8b - *[0-9a-f]+: 4fbbfab1 usdot v17\.2s, v21\.8b, v27\.4b\[3\] - *[0-9a-f]+: 4fa0f800 usdot v0\.2s, v0\.8b, v0\.4b\[3\] - *[0-9a-f]+: 4f9bf2b1 usdot v17\.2s, v21\.8b, v27\.4b\[0\] - *[0-9a-f]+: 4f80f000 usdot v0\.2s, v0\.8b, v0\.4b\[0\] - *[0-9a-f]+: 4f3bfab1 sudot v17\.2s, v21\.8b, v27\.4b\[3\] - *[0-9a-f]+: 4f20f800 sudot v0\.2s, v0\.8b, v0\.4b\[3\] - *[0-9a-f]+: 4f1bf2b1 sudot v17\.2s, v21\.8b, v27\.4b\[0\] - *[0-9a-f]+: 4f00f000 sudot v0\.2s, v0\.8b, v0\.4b\[0\] + *[0-9a-f]+: 0e9b9eb1 usdot v17\.2s, v21\.8b, v27\.8b + *[0-9a-f]+: 0e809c00 usdot v0\.2s, v0\.8b, v0\.8b + *[0-9a-f]+: 4e9b9eb1 usdot v17\.4s, v21\.16b, v27\.16b + *[0-9a-f]+: 4e809c00 usdot v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 0fbbfab1 usdot v17\.2s, v21\.8b, v27\.4b\[3\] + *[0-9a-f]+: 0fa0f800 usdot v0\.2s, v0\.8b, v0\.4b\[3\] + *[0-9a-f]+: 0f9bf2b1 usdot v17\.2s, v21\.8b, v27\.4b\[0\] + *[0-9a-f]+: 0f80f000 usdot v0\.2s, v0\.8b, v0\.4b\[0\] + *[0-9a-f]+: 4fbbfab1 usdot v17\.4s, v21\.16b, v27\.4b\[3\] + *[0-9a-f]+: 4fa0f800 usdot v0\.4s, v0\.16b, v0\.4b\[3\] + *[0-9a-f]+: 4f9bf2b1 usdot v17\.4s, v21\.16b, v27\.4b\[0\] + *[0-9a-f]+: 4f80f000 usdot v0\.4s, v0\.16b, v0\.4b\[0\] + *[0-9a-f]+: 0f3bfab1 sudot v17\.2s, v21\.8b, v27\.4b\[3\] + *[0-9a-f]+: 0f20f800 sudot v0\.2s, v0\.8b, v0\.4b\[3\] + *[0-9a-f]+: 0f1bf2b1 sudot v17\.2s, v21\.8b, v27\.4b\[0\] + *[0-9a-f]+: 0f00f000 sudot v0\.2s, v0\.8b, v0\.4b\[0\] + *[0-9a-f]+: 4f3bfab1 sudot v17\.4s, v21\.16b, v27\.4b\[3\] + *[0-9a-f]+: 4f20f800 sudot v0\.4s, v0\.16b, v0\.4b\[3\] + *[0-9a-f]+: 4f1bf2b1 sudot v17\.4s, v21\.16b, v27\.4b\[0\] + *[0-9a-f]+: 4f00f000 sudot v0\.4s, v0\.16b, v0\.4b\[0\] diff --git a/gas/testsuite/gas/aarch64/i8mm.s b/gas/testsuite/gas/aarch64/i8mm.s index 38f871da33..466aa9abc0 100644 --- a/gas/testsuite/gas/aarch64/i8mm.s +++ b/gas/testsuite/gas/aarch64/i8mm.s @@ -49,7 +49,15 @@ usdot v17.2s, v21.8b, v27.4b[3] usdot v0.2s, v0.8b, v0.4b[3] usdot v17.2s, v21.8b, v27.4b[0] usdot v0.2s, v0.8b, v0.4b[0] +usdot v17.4s, v21.16b, v27.4b[3] +usdot v0.4s, v0.16b, v0.4b[3] +usdot v17.4s, v21.16b, v27.4b[0] +usdot v0.4s, v0.16b, v0.4b[0] +sudot v17.2s, v21.8b, v27.4b[3] +sudot v0.2s, v0.8b, v0.4b[3] +sudot v17.2s, v21.8b, v27.4b[0] +sudot v0.2s, v0.8b, v0.4b[0] sudot v17.4s, v21.16b, v27.4b[3] sudot v0.4s, v0.16b, v0.4b[3] sudot v17.4s, v21.16b, v27.4b[0] diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ec6451271c..19a7b3f5c5 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2020-01-03 Jan Beulich + + * opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct SIMD + forms of SUDOT and USDOT. + 2020-01-03 Jan Beulich * opcodes/aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 3128d84130..2655ca5d56 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5092,9 +5092,9 @@ struct aarch64_opcode aarch64_opcode_table[] = INT8MATMUL_INSN ("smmla", 0x4e80a400, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0), INT8MATMUL_INSN ("ummla", 0x6e80a400, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0), INT8MATMUL_INSN ("usmmla", 0x4e80ac00, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0), - INT8MATMUL_INSN ("usdot", 0x4e809c00, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), - INT8MATMUL_INSN ("usdot", 0x4f80f000, 0xffc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), - INT8MATMUL_INSN ("sudot", 0x4f00f000, 0xffc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), + INT8MATMUL_INSN ("usdot", 0x0e809c00, 0xbfe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), + INT8MATMUL_INSN ("usdot", 0x0f80f000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), + INT8MATMUL_INSN ("sudot", 0x0f00f000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), /* BFloat instructions. */ BFLOAT16_SVE_INSNC ("bfdot", 0x64608000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),