From: Stefan Agner Date: Thu, 11 Feb 2016 00:02:25 +0000 (-0800) Subject: ARM: dts: vf610twr: assign Ethernet clock explicitly X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=6af2f61a293d3032dc5f59bea314355d6b7743e2;p=deliverable%2Flinux.git ARM: dts: vf610twr: assign Ethernet clock explicitly Assign Ethernet clock parents explicitly. The VF610 Tower Board uses the external Ethernet clock input which is connected to a 50MHz clock. The Vybrid SoC has two ethernet interfaces (fec0 and fec1) which use the same clock source (VF610_CLK_ENET). Therefore this parent configuration affects multiple consumer devices and need to be specified in the clock provider node. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index ce937b9fcf00..cdc100732514 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -128,6 +128,10 @@ &clks { clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; + assigned-clocks = <&clks VF610_CLK_ENET_SEL>, + <&clks VF610_CLK_ENET_TS_SEL>; + assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>, + <&clks VF610_CLK_ENET_EXT>; }; &dspi0 {