From: Samu Onkalo Date: Mon, 2 Aug 2010 11:21:40 +0000 (+0300) Subject: omap: dma: Support for prefetch in destination synchronizedtransfer X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=72a1179ed41e0fc6bd5eb58e02e8d230eba10e24;p=deliverable%2Flinux.git omap: dma: Support for prefetch in destination synchronizedtransfer Omap DMA controller can prefetch data in advance in case of destination synchronized data transfer. This may increase performance when target HW block doesn't have fifo. Data is waiting for transfer request in DMA fifo instead of read from memory. Signed-off-by: Samu Onkalo Signed-off-by: Tony Lindgren --- diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index f7f571e7987e..ec7eddf9e525 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -290,7 +290,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, val = dma_read(CCR(lch)); /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ - val &= ~((3 << 19) | 0x1f); + val &= ~((1 << 23) | (3 << 19) | 0x1f); val |= (dma_trigger & ~0x1f) << 14; val |= dma_trigger & 0x1f; @@ -304,11 +304,14 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, else val &= ~(1 << 18); - if (src_or_dst_synch) + if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) { + val &= ~(1 << 24); /* dest synch */ + val |= (1 << 23); /* Prefetch */ + } else if (src_or_dst_synch) { val |= 1 << 24; /* source synch */ - else + } else { val &= ~(1 << 24); /* dest synch */ - + } dma_write(val, CCR(lch)); } diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 02232ca2c37f..af3a03941add 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -345,6 +345,7 @@ #define OMAP_DMA_SYNC_BLOCK 0x02 #define OMAP_DMA_SYNC_PACKET 0x03 +#define OMAP_DMA_DST_SYNC_PREFETCH 0x02 #define OMAP_DMA_SRC_SYNC 0x01 #define OMAP_DMA_DST_SYNC 0x00