From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sat, 11 Oct 2008 17:09:45 +0000 (-0700)
Subject: Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=7cc4e87f912bbefa440a51856b8d076e5d1f554a;p=deliverable%2Flinux.git

Merge branch 'for-linus' of /home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
  [ARM] 5300/1: fixup spitz reset during boot
  [ARM] 5295/1: make ZONE_DMA optional
  [ARM] 5239/1: Palm Zire 72 power management support
  [ARM] 5298/1: Drop desc_handle_irq()
  [ARM] 5297/1: [KS8695] Fix two compile-time warnings
  [ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
  [ARM] pxa: allow multi-machine PCMCIA builds
  [ARM] pxa: add preliminary CPUFREQ support for PXA3xx
  [ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
  [ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
  [ARM] pxa/zylonite: add support for USB OHCI
  [ARM] ohci-pxa27x: use ioremap() and offset for register access
  [ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
  [ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
  [ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
  [ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
  [ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
  [ARM] pxa: simplify DMA register definitions
  [ARM] pxa: make additional DCSR bits valid for PXA3xx
  [ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
  ...

Fixed up conflicts in
	arch/arm/mach-versatile/core.c
	sound/soc/pxa/pxa2xx-ac97.c
	sound/soc/pxa/pxa2xx-i2s.c
manually.
---

7cc4e87f912bbefa440a51856b8d076e5d1f554a
diff --cc arch/arm/mach-versatile/core.c
index b638f10411e8,824121d52b8d..565e0ba0d67e
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@@ -28,11 -28,11 +28,11 @@@
  #include <linux/amba/clcd.h>
  #include <linux/clocksource.h>
  #include <linux/clockchips.h>
 +#include <linux/cnt32_to_63.h>
+ #include <linux/io.h>
  
 -#include <asm/cnt32_to_63.h>
  #include <asm/system.h>
  #include <mach/hardware.h>
- #include <asm/io.h>
  #include <asm/irq.h>
  #include <asm/leds.h>
  #include <asm/hardware/arm_timer.h>
diff --cc sound/soc/pxa/pxa2xx-i2s.c
index 39d19212f6d3,ad4c31ddb3d4..2fb58298513b
--- a/sound/soc/pxa/pxa2xx-i2s.c
+++ b/sound/soc/pxa/pxa2xx-i2s.c
@@@ -31,14 -30,45 +31,53 @@@
  #include "pxa2xx-pcm.h"
  #include "pxa2xx-i2s.h"
  
 +struct pxa2xx_gpio {
 +	u32 sys;
 +	u32	rx;
 +	u32 tx;
 +	u32 clk;
 +	u32 frm;
 +};
 +
+ /*
+  * I2S Controller Register and Bit Definitions
+  */
+ #define SACR0		__REG(0x40400000)  /* Global Control Register */
+ #define SACR1		__REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
+ #define SASR0		__REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+ #define SAIMR		__REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
+ #define SAICR		__REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
+ #define SADIV		__REG(0x40400060)  /* Audio Clock Divider Register. */
+ #define SADR		__REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
+ 
+ #define SACR0_RFTH(x)	((x) << 12)	/* Rx FIFO Interrupt or DMA Trigger Threshold */
+ #define SACR0_TFTH(x)	((x) << 8)	/* Tx FIFO Interrupt or DMA Trigger Threshold */
+ #define SACR0_STRF	(1 << 5)	/* FIFO Select for EFWR Special Function */
+ #define SACR0_EFWR	(1 << 4)	/* Enable EFWR Function  */
+ #define SACR0_RST	(1 << 3)	/* FIFO, i2s Register Reset */
+ #define SACR0_BCKD	(1 << 2) 	/* Bit Clock Direction */
+ #define SACR0_ENB	(1 << 0)	/* Enable I2S Link */
+ #define SACR1_ENLBF	(1 << 5)	/* Enable Loopback */
+ #define SACR1_DRPL	(1 << 4) 	/* Disable Replaying Function */
+ #define SACR1_DREC	(1 << 3)	/* Disable Recording Function */
+ #define SACR1_AMSL	(1 << 0)	/* Specify Alternate Mode */
+ 
+ #define SASR0_I2SOFF	(1 << 7)	/* Controller Status */
+ #define SASR0_ROR	(1 << 6)	/* Rx FIFO Overrun */
+ #define SASR0_TUR	(1 << 5)	/* Tx FIFO Underrun */
+ #define SASR0_RFS	(1 << 4)	/* Rx FIFO Service Request */
+ #define SASR0_TFS	(1 << 3)	/* Tx FIFO Service Request */
+ #define SASR0_BSY	(1 << 2)	/* I2S Busy */
+ #define SASR0_RNE	(1 << 1)	/* Rx FIFO Not Empty */
+ #define SASR0_TNF	(1 << 0) 	/* Tx FIFO Not Empty */
+ 
+ #define SAICR_ROR	(1 << 6)	/* Clear Rx FIFO Overrun Interrupt */
+ #define SAICR_TUR	(1 << 5)	/* Clear Tx FIFO Underrun Interrupt */
+ 
+ #define SAIMR_ROR	(1 << 6)	/* Enable Rx FIFO Overrun Condition Interrupt */
+ #define SAIMR_TUR	(1 << 5)	/* Enable Tx FIFO Underrun Condition Interrupt */
+ #define SAIMR_RFS	(1 << 4)	/* Enable Rx FIFO Service Interrupt */
+ #define SAIMR_TFS	(1 << 3)	/* Enable Tx FIFO Service Interrupt */
  
  struct pxa_i2s_port {
  	u32 sadiv;