From: Maciej W. Rozycki Date: Wed, 10 Aug 2011 22:52:03 +0000 (+0000) Subject: * gas/mips/micromips@mips5.d: Rename to... X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=85bb418f5ea3ed7e6eed54c45d2e85ee3ba2f1d4;p=deliverable%2Fbinutils-gdb.git * gas/mips/micromips@mips5.d: Rename to... * gas/mips/micromips@mips5-fp.d: ... this. * gas/mips/mips5.d: Rename to... * gas/mips/mips5-fp.d: ... this. * gas/mips/mips5.l: Rename to... * gas/mips/mips5-fp.l: ... this. * gas/mips/mips5.s: Rename to... * gas/mips/mips5-fp.s: ... this. * gas/mips/mips.exp: Update accordingly. --- diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index d447a651d1..19d71aed31 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,15 @@ +2011-08-10 Maciej W. Rozycki + + * gas/mips/micromips@mips5.d: Rename to... + * gas/mips/micromips@mips5-fp.d: ... this. + * gas/mips/mips5.d: Rename to... + * gas/mips/mips5-fp.d: ... this. + * gas/mips/mips5.l: Rename to... + * gas/mips/mips5-fp.l: ... this. + * gas/mips/mips5.s: Rename to... + * gas/mips/mips5-fp.s: ... this. + * gas/mips/mips.exp: Update accordingly. + 2011-08-10 Maciej W. Rozycki * gas/mips/mips.exp: Define new "fpisa3", "fpisa4" and "fpisa5" diff --git a/gas/testsuite/gas/mips/micromips@mips5-fp.d b/gas/testsuite/gas/mips/micromips@mips5-fp.d new file mode 100644 index 0000000000..f9afb62a88 --- /dev/null +++ b/gas/testsuite/gas/mips/micromips@mips5-fp.d @@ -0,0 +1,69 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric +#name: MIPS mips5 instructions +#source: mips5-fp.s +#stderr: mips5-fp.l + +# Check MIPS V instruction assembly (microMIPS). + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 5402 437b abs\.ps \$f0,\$f2 +[0-9a-f]+ <[^>]*> 54c4 1230 add\.ps \$f2,\$f4,\$f6 +[0-9a-f]+ <[^>]*> 5548 30d9 alnv\.ps \$f6,\$f8,\$f10,\$3 +[0-9a-f]+ <[^>]*> 5548 08bc c\.eq\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 48bc c\.eq\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 083c c\.f\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 483c c\.f\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 0bbc c\.le\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 4bbc c\.le\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 0b3c c\.lt\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 4b3c c\.lt\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 0b7c c\.nge\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 4b7c c\.nge\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 0afc c\.ngl\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 4afc c\.ngl\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 0a7c c\.ngle\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 4a7c c\.ngle\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 0bfc c\.ngt\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 4bfc c\.ngt\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 09bc c\.ole\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 49bc c\.ole\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 093c c\.olt\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 493c c\.olt\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 0abc c\.seq\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 4abc c\.seq\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 0a3c c\.sf\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 4a3c c\.sf\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 08fc c\.ueq\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 48fc c\.ueq\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 09fc c\.ule\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 49fc c\.ule\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 097c c\.ult\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 497c c\.ult\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 5548 087c c\.un\.ps \$f8,\$f10 +[0-9a-f]+ <[^>]*> 558a 487c c\.un\.ps \$fcc2,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 560e 6180 cvt\.ps\.s \$f12,\$f14,\$f16 +[0-9a-f]+ <[^>]*> 5612 213b cvt\.s\.pl \$f16,\$f18 +[0-9a-f]+ <[^>]*> 5654 293b cvt\.s\.pu \$f18,\$f20 +[0-9a-f]+ <[^>]*> 5485 a148 luxc1 \$f20,\$4\(\$5\) +[0-9a-f]+ <[^>]*> 5758 a591 madd\.ps \$f20,\$f22,\$f24,\$f26 +[0-9a-f]+ <[^>]*> 571a 407b mov\.ps \$f24,\$f26 +[0-9a-f]+ <[^>]*> 575c 4420 movf\.ps \$f26,\$f28,\$fcc2 +[0-9a-f]+ <[^>]*> 547c d238 movn\.ps \$f26,\$f28,\$3 +[0-9a-f]+ <[^>]*> 579e 8460 movt\.ps \$f28,\$f30,\$fcc4 +[0-9a-f]+ <[^>]*> 54be e278 movz\.ps \$f28,\$f30,\$5 +[0-9a-f]+ <[^>]*> 5482 f031 msub\.ps \$f30,\$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 54c4 12b0 mul\.ps \$f2,\$f4,\$f6 +[0-9a-f]+ <[^>]*> 54c8 4b7b neg\.ps \$f6,\$f8 +[0-9a-f]+ <[^>]*> 558a 3212 nmadd\.ps \$f6,\$f8,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 558a 3232 nmsub\.ps \$f6,\$f8,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 55cc 5080 pll\.ps \$f10,\$f12,\$f14 +[0-9a-f]+ <[^>]*> 5650 70c0 plu\.ps \$f14,\$f16,\$f18 +[0-9a-f]+ <[^>]*> 5692 8100 pul\.ps \$f16,\$f18,\$f20 +[0-9a-f]+ <[^>]*> 5716 a140 puu\.ps \$f20,\$f22,\$f24 +[0-9a-f]+ <[^>]*> 5758 b270 sub\.ps \$f22,\$f24,\$f26 +[0-9a-f]+ <[^>]*> 54c7 d188 suxc1 \$f26,\$6\(\$7\) +[0-9a-f]+ <[^>]*> 558a 68bc c\.eq\.ps \$fcc3,\$f10,\$f12 +[0-9a-f]+ <[^>]*> 575c 6420 movf\.ps \$f26,\$f28,\$fcc3 + \.\.\. diff --git a/gas/testsuite/gas/mips/micromips@mips5.d b/gas/testsuite/gas/mips/micromips@mips5.d deleted file mode 100644 index 4c8099b63e..0000000000 --- a/gas/testsuite/gas/mips/micromips@mips5.d +++ /dev/null @@ -1,69 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric -#name: MIPS mips5 instructions -#source: mips5.s -#stderr: mips5.l - -# Check MIPS V instruction assembly (microMIPS). - -.*: +file format .*mips.* - -Disassembly of section \.text: -[0-9a-f]+ <[^>]*> 5402 437b abs\.ps \$f0,\$f2 -[0-9a-f]+ <[^>]*> 54c4 1230 add\.ps \$f2,\$f4,\$f6 -[0-9a-f]+ <[^>]*> 5548 30d9 alnv\.ps \$f6,\$f8,\$f10,\$3 -[0-9a-f]+ <[^>]*> 5548 08bc c\.eq\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 48bc c\.eq\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 083c c\.f\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 483c c\.f\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 0bbc c\.le\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 4bbc c\.le\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 0b3c c\.lt\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 4b3c c\.lt\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 0b7c c\.nge\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 4b7c c\.nge\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 0afc c\.ngl\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 4afc c\.ngl\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 0a7c c\.ngle\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 4a7c c\.ngle\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 0bfc c\.ngt\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 4bfc c\.ngt\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 09bc c\.ole\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 49bc c\.ole\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 093c c\.olt\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 493c c\.olt\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 0abc c\.seq\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 4abc c\.seq\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 0a3c c\.sf\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 4a3c c\.sf\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 08fc c\.ueq\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 48fc c\.ueq\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 09fc c\.ule\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 49fc c\.ule\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 097c c\.ult\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 497c c\.ult\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 5548 087c c\.un\.ps \$f8,\$f10 -[0-9a-f]+ <[^>]*> 558a 487c c\.un\.ps \$fcc2,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 560e 6180 cvt\.ps\.s \$f12,\$f14,\$f16 -[0-9a-f]+ <[^>]*> 5612 213b cvt\.s\.pl \$f16,\$f18 -[0-9a-f]+ <[^>]*> 5654 293b cvt\.s\.pu \$f18,\$f20 -[0-9a-f]+ <[^>]*> 5485 a148 luxc1 \$f20,\$4\(\$5\) -[0-9a-f]+ <[^>]*> 5758 a591 madd\.ps \$f20,\$f22,\$f24,\$f26 -[0-9a-f]+ <[^>]*> 571a 407b mov\.ps \$f24,\$f26 -[0-9a-f]+ <[^>]*> 575c 4420 movf\.ps \$f26,\$f28,\$fcc2 -[0-9a-f]+ <[^>]*> 547c d238 movn\.ps \$f26,\$f28,\$3 -[0-9a-f]+ <[^>]*> 579e 8460 movt\.ps \$f28,\$f30,\$fcc4 -[0-9a-f]+ <[^>]*> 54be e278 movz\.ps \$f28,\$f30,\$5 -[0-9a-f]+ <[^>]*> 5482 f031 msub\.ps \$f30,\$f0,\$f2,\$f4 -[0-9a-f]+ <[^>]*> 54c4 12b0 mul\.ps \$f2,\$f4,\$f6 -[0-9a-f]+ <[^>]*> 54c8 4b7b neg\.ps \$f6,\$f8 -[0-9a-f]+ <[^>]*> 558a 3212 nmadd\.ps \$f6,\$f8,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 558a 3232 nmsub\.ps \$f6,\$f8,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 55cc 5080 pll\.ps \$f10,\$f12,\$f14 -[0-9a-f]+ <[^>]*> 5650 70c0 plu\.ps \$f14,\$f16,\$f18 -[0-9a-f]+ <[^>]*> 5692 8100 pul\.ps \$f16,\$f18,\$f20 -[0-9a-f]+ <[^>]*> 5716 a140 puu\.ps \$f20,\$f22,\$f24 -[0-9a-f]+ <[^>]*> 5758 b270 sub\.ps \$f22,\$f24,\$f26 -[0-9a-f]+ <[^>]*> 54c7 d188 suxc1 \$f26,\$6\(\$7\) -[0-9a-f]+ <[^>]*> 558a 68bc c\.eq\.ps \$fcc3,\$f10,\$f12 -[0-9a-f]+ <[^>]*> 575c 6420 movf\.ps \$f26,\$f28,\$fcc3 - \.\.\. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 4512518270..a2b8f6cc2d 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -634,7 +634,7 @@ if { [istarget mips*-*-vxworks*] } { [mips_arch_list_matching mips4] run_list_test_arches "mips4-branch-likely" "-32 -msoft-float" \ [mips_arch_list_matching mips4] - run_dump_test_arches "mips5" [mips_arch_list_matching fpisa5] + run_dump_test_arches "mips5-fp" [mips_arch_list_matching fpisa5] run_dump_test "mul" run_dump_test_arches "rol" [mips_arch_list_matching mips1 !ror] diff --git a/gas/testsuite/gas/mips/mips5-fp.d b/gas/testsuite/gas/mips/mips5-fp.d new file mode 100644 index 0000000000..a114a0b910 --- /dev/null +++ b/gas/testsuite/gas/mips/mips5-fp.d @@ -0,0 +1,68 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric +#name: MIPS mips5 instructions +#stderr: mips5-fp.l + +# Check MIPS V instruction assembly + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+0000 <[^>]*> 46c01005 abs\.ps \$f0,\$f2 +0+0004 <[^>]*> 46c62080 add\.ps \$f2,\$f4,\$f6 +0+0008 <[^>]*> 4c6a419e alnv\.ps \$f6,\$f8,\$f10,\$3 +0+000c <[^>]*> 46ca4032 c\.eq\.ps \$f8,\$f10 +0+0010 <[^>]*> 46cc5232 c\.eq\.ps \$fcc2,\$f10,\$f12 +0+0014 <[^>]*> 46ca4030 c\.f\.ps \$f8,\$f10 +0+0018 <[^>]*> 46cc5230 c\.f\.ps \$fcc2,\$f10,\$f12 +0+001c <[^>]*> 46ca403e c\.le\.ps \$f8,\$f10 +0+0020 <[^>]*> 46cc523e c\.le\.ps \$fcc2,\$f10,\$f12 +0+0024 <[^>]*> 46ca403c c\.lt\.ps \$f8,\$f10 +0+0028 <[^>]*> 46cc523c c\.lt\.ps \$fcc2,\$f10,\$f12 +0+002c <[^>]*> 46ca403d c\.nge\.ps \$f8,\$f10 +0+0030 <[^>]*> 46cc523d c\.nge\.ps \$fcc2,\$f10,\$f12 +0+0034 <[^>]*> 46ca403b c\.ngl\.ps \$f8,\$f10 +0+0038 <[^>]*> 46cc523b c\.ngl\.ps \$fcc2,\$f10,\$f12 +0+003c <[^>]*> 46ca4039 c\.ngle\.ps \$f8,\$f10 +0+0040 <[^>]*> 46cc5239 c\.ngle\.ps \$fcc2,\$f10,\$f12 +0+0044 <[^>]*> 46ca403f c\.ngt\.ps \$f8,\$f10 +0+0048 <[^>]*> 46cc523f c\.ngt\.ps \$fcc2,\$f10,\$f12 +0+004c <[^>]*> 46ca4036 c\.ole\.ps \$f8,\$f10 +0+0050 <[^>]*> 46cc5236 c\.ole\.ps \$fcc2,\$f10,\$f12 +0+0054 <[^>]*> 46ca4034 c\.olt\.ps \$f8,\$f10 +0+0058 <[^>]*> 46cc5234 c\.olt\.ps \$fcc2,\$f10,\$f12 +0+005c <[^>]*> 46ca403a c\.seq\.ps \$f8,\$f10 +0+0060 <[^>]*> 46cc523a c\.seq\.ps \$fcc2,\$f10,\$f12 +0+0064 <[^>]*> 46ca4038 c\.sf\.ps \$f8,\$f10 +0+0068 <[^>]*> 46cc5238 c\.sf\.ps \$fcc2,\$f10,\$f12 +0+006c <[^>]*> 46ca4033 c\.ueq\.ps \$f8,\$f10 +0+0070 <[^>]*> 46cc5233 c\.ueq\.ps \$fcc2,\$f10,\$f12 +0+0074 <[^>]*> 46ca4037 c\.ule\.ps \$f8,\$f10 +0+0078 <[^>]*> 46cc5237 c\.ule\.ps \$fcc2,\$f10,\$f12 +0+007c <[^>]*> 46ca4035 c\.ult\.ps \$f8,\$f10 +0+0080 <[^>]*> 46cc5235 c\.ult\.ps \$fcc2,\$f10,\$f12 +0+0084 <[^>]*> 46ca4031 c\.un\.ps \$f8,\$f10 +0+0088 <[^>]*> 46cc5231 c\.un\.ps \$fcc2,\$f10,\$f12 +0+008c <[^>]*> 46107326 cvt\.ps\.s \$f12,\$f14,\$f16 +0+0090 <[^>]*> 46c09428 cvt\.s\.pl \$f16,\$f18 +0+0094 <[^>]*> 46c0a4a0 cvt\.s\.pu \$f18,\$f20 +0+0098 <[^>]*> 4ca40505 luxc1 \$f20,\$4\(\$5\) +0+009c <[^>]*> 4edac526 madd\.ps \$f20,\$f22,\$f24,\$f26 +0+00a0 <[^>]*> 46c0d606 mov\.ps \$f24,\$f26 +0+00a4 <[^>]*> 46c8e691 movf\.ps \$f26,\$f28,\$fcc2 +0+00a8 <[^>]*> 46c3e693 movn\.ps \$f26,\$f28,\$3 +0+00ac <[^>]*> 46d1f711 movt\.ps \$f28,\$f30,\$fcc4 +0+00b0 <[^>]*> 46c5f712 movz\.ps \$f28,\$f30,\$5 +0+00b4 <[^>]*> 4c0417ae msub\.ps \$f30,\$f0,\$f2,\$f4 +0+00b8 <[^>]*> 46c62082 mul\.ps \$f2,\$f4,\$f6 +0+00bc <[^>]*> 46c04187 neg\.ps \$f6,\$f8 +0+00c0 <[^>]*> 4d0c51b6 nmadd\.ps \$f6,\$f8,\$f10,\$f12 +0+00c4 <[^>]*> 4d0c51be nmsub\.ps \$f6,\$f8,\$f10,\$f12 +0+00c8 <[^>]*> 46ce62ac pll\.ps \$f10,\$f12,\$f14 +0+00cc <[^>]*> 46d283ad plu\.ps \$f14,\$f16,\$f18 +0+00d0 <[^>]*> 46d4942e pul\.ps \$f16,\$f18,\$f20 +0+00d4 <[^>]*> 46d8b52f puu\.ps \$f20,\$f22,\$f24 +0+00d8 <[^>]*> 46dac581 sub\.ps \$f22,\$f24,\$f26 +0+00dc <[^>]*> 4ce6d00d suxc1 \$f26,\$6\(\$7\) +0+00e0 <[^>]*> 46cc5332 c\.eq\.ps \$fcc3,\$f10,\$f12 +0+00e4 <[^>]*> 46cce691 movf\.ps \$f26,\$f28,\$fcc3 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips5-fp.l b/gas/testsuite/gas/mips/mips5-fp.l new file mode 100644 index 0000000000..bb6ed49ddf --- /dev/null +++ b/gas/testsuite/gas/mips/mips5-fp.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*:61: Warning: Condition code register should be even for c.eq.ps, was 3 +.*:62: Warning: Condition code register should be even for movf.ps, was 3 diff --git a/gas/testsuite/gas/mips/mips5-fp.s b/gas/testsuite/gas/mips/mips5-fp.s new file mode 100644 index 0000000000..70b844e578 --- /dev/null +++ b/gas/testsuite/gas/mips/mips5-fp.s @@ -0,0 +1,65 @@ +# Source file used to test -mips5 instructions. + +text_label: + abs.ps $f0, $f2 + add.ps $f2, $f4, $f6 + alnv.ps $f6, $f8, $f10, $3 + c.eq.ps $f8, $f10 + c.eq.ps $fcc2, $f10, $f12 + c.f.ps $f8, $f10 + c.f.ps $fcc2, $f10, $f12 + c.le.ps $f8, $f10 + c.le.ps $fcc2, $f10, $f12 + c.lt.ps $f8, $f10 + c.lt.ps $fcc2, $f10, $f12 + c.nge.ps $f8, $f10 + c.nge.ps $fcc2, $f10, $f12 + c.ngl.ps $f8, $f10 + c.ngl.ps $fcc2, $f10, $f12 + c.ngle.ps $f8, $f10 + c.ngle.ps $fcc2, $f10, $f12 + c.ngt.ps $f8, $f10 + c.ngt.ps $fcc2, $f10, $f12 + c.ole.ps $f8, $f10 + c.ole.ps $fcc2, $f10, $f12 + c.olt.ps $f8, $f10 + c.olt.ps $fcc2, $f10, $f12 + c.seq.ps $f8, $f10 + c.seq.ps $fcc2, $f10, $f12 + c.sf.ps $f8, $f10 + c.sf.ps $fcc2, $f10, $f12 + c.ueq.ps $f8, $f10 + c.ueq.ps $fcc2, $f10, $f12 + c.ule.ps $f8, $f10 + c.ule.ps $fcc2, $f10, $f12 + c.ult.ps $f8, $f10 + c.ult.ps $fcc2, $f10, $f12 + c.un.ps $f8, $f10 + c.un.ps $fcc2, $f10, $f12 + cvt.ps.s $f12, $f14, $f16 + cvt.s.pl $f16, $f18 + cvt.s.pu $f18, $f20 + luxc1 $f20, $4($5) + madd.ps $f20, $f22, $f24, $f26 + mov.ps $f24, $f26 + movf.ps $f26, $f28, $fcc2 + movn.ps $f26, $f28, $3 + movt.ps $f28, $f30, $fcc4 + movz.ps $f28, $f30, $5 + msub.ps $f30, $f0, $f2, $f4 + mul.ps $f2, $f4, $f6 + neg.ps $f6, $f8 + nmadd.ps $f6, $f8, $f10, $f12 + nmsub.ps $f6, $f8, $f10, $f12 + pll.ps $f10, $f12, $f14 + plu.ps $f14, $f16, $f18 + pul.ps $f16, $f18, $f20 + puu.ps $f20, $f22, $f24 + sub.ps $f22, $f24, $f26 + suxc1 $f26, $6($7) + + c.eq.ps $fcc3, $f10, $f12 # warns + movf.ps $f26, $f28, $fcc3 # warns + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/gas/testsuite/gas/mips/mips5.d b/gas/testsuite/gas/mips/mips5.d deleted file mode 100644 index e313f56447..0000000000 --- a/gas/testsuite/gas/mips/mips5.d +++ /dev/null @@ -1,68 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric -#name: MIPS mips5 instructions -#stderr: mips5.l - -# Check MIPS V instruction assembly - -.*: +file format .*mips.* - -Disassembly of section \.text: -0+0000 <[^>]*> 46c01005 abs\.ps \$f0,\$f2 -0+0004 <[^>]*> 46c62080 add\.ps \$f2,\$f4,\$f6 -0+0008 <[^>]*> 4c6a419e alnv\.ps \$f6,\$f8,\$f10,\$3 -0+000c <[^>]*> 46ca4032 c\.eq\.ps \$f8,\$f10 -0+0010 <[^>]*> 46cc5232 c\.eq\.ps \$fcc2,\$f10,\$f12 -0+0014 <[^>]*> 46ca4030 c\.f\.ps \$f8,\$f10 -0+0018 <[^>]*> 46cc5230 c\.f\.ps \$fcc2,\$f10,\$f12 -0+001c <[^>]*> 46ca403e c\.le\.ps \$f8,\$f10 -0+0020 <[^>]*> 46cc523e c\.le\.ps \$fcc2,\$f10,\$f12 -0+0024 <[^>]*> 46ca403c c\.lt\.ps \$f8,\$f10 -0+0028 <[^>]*> 46cc523c c\.lt\.ps \$fcc2,\$f10,\$f12 -0+002c <[^>]*> 46ca403d c\.nge\.ps \$f8,\$f10 -0+0030 <[^>]*> 46cc523d c\.nge\.ps \$fcc2,\$f10,\$f12 -0+0034 <[^>]*> 46ca403b c\.ngl\.ps \$f8,\$f10 -0+0038 <[^>]*> 46cc523b c\.ngl\.ps \$fcc2,\$f10,\$f12 -0+003c <[^>]*> 46ca4039 c\.ngle\.ps \$f8,\$f10 -0+0040 <[^>]*> 46cc5239 c\.ngle\.ps \$fcc2,\$f10,\$f12 -0+0044 <[^>]*> 46ca403f c\.ngt\.ps \$f8,\$f10 -0+0048 <[^>]*> 46cc523f c\.ngt\.ps \$fcc2,\$f10,\$f12 -0+004c <[^>]*> 46ca4036 c\.ole\.ps \$f8,\$f10 -0+0050 <[^>]*> 46cc5236 c\.ole\.ps \$fcc2,\$f10,\$f12 -0+0054 <[^>]*> 46ca4034 c\.olt\.ps \$f8,\$f10 -0+0058 <[^>]*> 46cc5234 c\.olt\.ps \$fcc2,\$f10,\$f12 -0+005c <[^>]*> 46ca403a c\.seq\.ps \$f8,\$f10 -0+0060 <[^>]*> 46cc523a c\.seq\.ps \$fcc2,\$f10,\$f12 -0+0064 <[^>]*> 46ca4038 c\.sf\.ps \$f8,\$f10 -0+0068 <[^>]*> 46cc5238 c\.sf\.ps \$fcc2,\$f10,\$f12 -0+006c <[^>]*> 46ca4033 c\.ueq\.ps \$f8,\$f10 -0+0070 <[^>]*> 46cc5233 c\.ueq\.ps \$fcc2,\$f10,\$f12 -0+0074 <[^>]*> 46ca4037 c\.ule\.ps \$f8,\$f10 -0+0078 <[^>]*> 46cc5237 c\.ule\.ps \$fcc2,\$f10,\$f12 -0+007c <[^>]*> 46ca4035 c\.ult\.ps \$f8,\$f10 -0+0080 <[^>]*> 46cc5235 c\.ult\.ps \$fcc2,\$f10,\$f12 -0+0084 <[^>]*> 46ca4031 c\.un\.ps \$f8,\$f10 -0+0088 <[^>]*> 46cc5231 c\.un\.ps \$fcc2,\$f10,\$f12 -0+008c <[^>]*> 46107326 cvt\.ps\.s \$f12,\$f14,\$f16 -0+0090 <[^>]*> 46c09428 cvt\.s\.pl \$f16,\$f18 -0+0094 <[^>]*> 46c0a4a0 cvt\.s\.pu \$f18,\$f20 -0+0098 <[^>]*> 4ca40505 luxc1 \$f20,\$4\(\$5\) -0+009c <[^>]*> 4edac526 madd\.ps \$f20,\$f22,\$f24,\$f26 -0+00a0 <[^>]*> 46c0d606 mov\.ps \$f24,\$f26 -0+00a4 <[^>]*> 46c8e691 movf\.ps \$f26,\$f28,\$fcc2 -0+00a8 <[^>]*> 46c3e693 movn\.ps \$f26,\$f28,\$3 -0+00ac <[^>]*> 46d1f711 movt\.ps \$f28,\$f30,\$fcc4 -0+00b0 <[^>]*> 46c5f712 movz\.ps \$f28,\$f30,\$5 -0+00b4 <[^>]*> 4c0417ae msub\.ps \$f30,\$f0,\$f2,\$f4 -0+00b8 <[^>]*> 46c62082 mul\.ps \$f2,\$f4,\$f6 -0+00bc <[^>]*> 46c04187 neg\.ps \$f6,\$f8 -0+00c0 <[^>]*> 4d0c51b6 nmadd\.ps \$f6,\$f8,\$f10,\$f12 -0+00c4 <[^>]*> 4d0c51be nmsub\.ps \$f6,\$f8,\$f10,\$f12 -0+00c8 <[^>]*> 46ce62ac pll\.ps \$f10,\$f12,\$f14 -0+00cc <[^>]*> 46d283ad plu\.ps \$f14,\$f16,\$f18 -0+00d0 <[^>]*> 46d4942e pul\.ps \$f16,\$f18,\$f20 -0+00d4 <[^>]*> 46d8b52f puu\.ps \$f20,\$f22,\$f24 -0+00d8 <[^>]*> 46dac581 sub\.ps \$f22,\$f24,\$f26 -0+00dc <[^>]*> 4ce6d00d suxc1 \$f26,\$6\(\$7\) -0+00e0 <[^>]*> 46cc5332 c\.eq\.ps \$fcc3,\$f10,\$f12 -0+00e4 <[^>]*> 46cce691 movf\.ps \$f26,\$f28,\$fcc3 - \.\.\. diff --git a/gas/testsuite/gas/mips/mips5.l b/gas/testsuite/gas/mips/mips5.l deleted file mode 100644 index bb6ed49ddf..0000000000 --- a/gas/testsuite/gas/mips/mips5.l +++ /dev/null @@ -1,3 +0,0 @@ -.*: Assembler messages: -.*:61: Warning: Condition code register should be even for c.eq.ps, was 3 -.*:62: Warning: Condition code register should be even for movf.ps, was 3 diff --git a/gas/testsuite/gas/mips/mips5.s b/gas/testsuite/gas/mips/mips5.s deleted file mode 100644 index 70b844e578..0000000000 --- a/gas/testsuite/gas/mips/mips5.s +++ /dev/null @@ -1,65 +0,0 @@ -# Source file used to test -mips5 instructions. - -text_label: - abs.ps $f0, $f2 - add.ps $f2, $f4, $f6 - alnv.ps $f6, $f8, $f10, $3 - c.eq.ps $f8, $f10 - c.eq.ps $fcc2, $f10, $f12 - c.f.ps $f8, $f10 - c.f.ps $fcc2, $f10, $f12 - c.le.ps $f8, $f10 - c.le.ps $fcc2, $f10, $f12 - c.lt.ps $f8, $f10 - c.lt.ps $fcc2, $f10, $f12 - c.nge.ps $f8, $f10 - c.nge.ps $fcc2, $f10, $f12 - c.ngl.ps $f8, $f10 - c.ngl.ps $fcc2, $f10, $f12 - c.ngle.ps $f8, $f10 - c.ngle.ps $fcc2, $f10, $f12 - c.ngt.ps $f8, $f10 - c.ngt.ps $fcc2, $f10, $f12 - c.ole.ps $f8, $f10 - c.ole.ps $fcc2, $f10, $f12 - c.olt.ps $f8, $f10 - c.olt.ps $fcc2, $f10, $f12 - c.seq.ps $f8, $f10 - c.seq.ps $fcc2, $f10, $f12 - c.sf.ps $f8, $f10 - c.sf.ps $fcc2, $f10, $f12 - c.ueq.ps $f8, $f10 - c.ueq.ps $fcc2, $f10, $f12 - c.ule.ps $f8, $f10 - c.ule.ps $fcc2, $f10, $f12 - c.ult.ps $f8, $f10 - c.ult.ps $fcc2, $f10, $f12 - c.un.ps $f8, $f10 - c.un.ps $fcc2, $f10, $f12 - cvt.ps.s $f12, $f14, $f16 - cvt.s.pl $f16, $f18 - cvt.s.pu $f18, $f20 - luxc1 $f20, $4($5) - madd.ps $f20, $f22, $f24, $f26 - mov.ps $f24, $f26 - movf.ps $f26, $f28, $fcc2 - movn.ps $f26, $f28, $3 - movt.ps $f28, $f30, $fcc4 - movz.ps $f28, $f30, $5 - msub.ps $f30, $f0, $f2, $f4 - mul.ps $f2, $f4, $f6 - neg.ps $f6, $f8 - nmadd.ps $f6, $f8, $f10, $f12 - nmsub.ps $f6, $f8, $f10, $f12 - pll.ps $f10, $f12, $f14 - plu.ps $f14, $f16, $f18 - pul.ps $f16, $f18, $f20 - puu.ps $f20, $f22, $f24 - sub.ps $f22, $f24, $f26 - suxc1 $f26, $6($7) - - c.eq.ps $fcc3, $f10, $f12 # warns - movf.ps $f26, $f28, $fcc3 # warns - -# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... - .space 8