From: Doug Evans Date: Wed, 10 Feb 1999 23:39:09 +0000 (+0000) Subject: * sparc-desc.c: New file. X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=8d3b723419385f02d8212f93d1b42d81cd21c2ce;p=deliverable%2Fbinutils-gdb.git * sparc-desc.c: New file. * sparc-desc.h: New file. * sparc-opc.h: New file. * decode64.c: New file. * decode64.h: New file. * sem64.c: New file. * cpu64.c: New file. * cpu64.h: New file. * model64.h: New file. * mloop64.in: New file. * regs64.h: New file. * trap64.c: New file. * cpu32.h,decode32.c,decode32.h,model32.c,sem32.c: Rebuild. --- diff --git a/sim/sparc/.Sanitize b/sim/sparc/.Sanitize index e1076adf65..2701b9525e 100644 --- a/sim/sparc/.Sanitize +++ b/sim/sparc/.Sanitize @@ -33,17 +33,25 @@ configure configure.in cpu32.c cpu32.h +cpu64.c +cpu64.h cpuall.h decode32.c decode32.h +decode64.c +decode64.h dev32.c dev32.h dev64.c dev64.h mloop32.in +mloop64.in model32.c +model64.c regs32.h +regs64.h sem32.c +sem64.c sim-if.c sim-main.h sparc-sim.h @@ -53,6 +61,7 @@ sparc64.c tconfig.in trap32.c trap32.h +trap64.c trap64.h Things-to-lose: diff --git a/sim/sparc/cpu64.c b/sim/sparc/cpu64.c new file mode 100644 index 0000000000..8d27e75d39 --- /dev/null +++ b/sim/sparc/cpu64.c @@ -0,0 +1,759 @@ +/* Misc. support for CPU family sparc64. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#define WANT_CPU sparc64 +#define WANT_CPU_SPARC64 + +#include "sim-main.h" + +/* Get the value of h-pc. */ + +USI +sparc64_h_pc_get (SIM_CPU *current_cpu) +{ + return CPU (h_pc); +} + +/* Set a value for h-pc. */ + +void +sparc64_h_pc_set (SIM_CPU *current_cpu, USI newval) +{ + CPU (h_pc) = newval; +} + +/* Get the value of h-npc. */ + +SI +sparc64_h_npc_get (SIM_CPU *current_cpu) +{ + return CPU (h_npc); +} + +/* Set a value for h-npc. */ + +void +sparc64_h_npc_set (SIM_CPU *current_cpu, SI newval) +{ + CPU (h_npc) = newval; +} + +/* Get the value of h-gr. */ + +SI +sparc64_h_gr_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_GR (regno); +} + +/* Set a value for h-gr. */ + +void +sparc64_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) +{ + SET_H_GR (regno, newval); +} + +/* Get the value of h-icc-c. */ + +BI +sparc64_h_icc_c_get (SIM_CPU *current_cpu) +{ + return CPU (h_icc_c); +} + +/* Set a value for h-icc-c. */ + +void +sparc64_h_icc_c_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_icc_c) = newval; +} + +/* Get the value of h-icc-n. */ + +BI +sparc64_h_icc_n_get (SIM_CPU *current_cpu) +{ + return CPU (h_icc_n); +} + +/* Set a value for h-icc-n. */ + +void +sparc64_h_icc_n_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_icc_n) = newval; +} + +/* Get the value of h-icc-v. */ + +BI +sparc64_h_icc_v_get (SIM_CPU *current_cpu) +{ + return CPU (h_icc_v); +} + +/* Set a value for h-icc-v. */ + +void +sparc64_h_icc_v_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_icc_v) = newval; +} + +/* Get the value of h-icc-z. */ + +BI +sparc64_h_icc_z_get (SIM_CPU *current_cpu) +{ + return CPU (h_icc_z); +} + +/* Set a value for h-icc-z. */ + +void +sparc64_h_icc_z_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_icc_z) = newval; +} + +/* Get the value of h-xcc-c. */ + +BI +sparc64_h_xcc_c_get (SIM_CPU *current_cpu) +{ + return CPU (h_xcc_c); +} + +/* Set a value for h-xcc-c. */ + +void +sparc64_h_xcc_c_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_xcc_c) = newval; +} + +/* Get the value of h-xcc-n. */ + +BI +sparc64_h_xcc_n_get (SIM_CPU *current_cpu) +{ + return CPU (h_xcc_n); +} + +/* Set a value for h-xcc-n. */ + +void +sparc64_h_xcc_n_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_xcc_n) = newval; +} + +/* Get the value of h-xcc-v. */ + +BI +sparc64_h_xcc_v_get (SIM_CPU *current_cpu) +{ + return CPU (h_xcc_v); +} + +/* Set a value for h-xcc-v. */ + +void +sparc64_h_xcc_v_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_xcc_v) = newval; +} + +/* Get the value of h-xcc-z. */ + +BI +sparc64_h_xcc_z_get (SIM_CPU *current_cpu) +{ + return CPU (h_xcc_z); +} + +/* Set a value for h-xcc-z. */ + +void +sparc64_h_xcc_z_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_xcc_z) = newval; +} + +/* Get the value of h-y. */ + +SI +sparc64_h_y_get (SIM_CPU *current_cpu) +{ + return GET_H_Y (); +} + +/* Set a value for h-y. */ + +void +sparc64_h_y_set (SIM_CPU *current_cpu, SI newval) +{ + SET_H_Y (newval); +} + +/* Get the value of h-asr. */ + +SI +sparc64_h_asr_get (SIM_CPU *current_cpu, UINT regno) +{ + return CPU (h_asr[regno]); +} + +/* Set a value for h-asr. */ + +void +sparc64_h_asr_set (SIM_CPU *current_cpu, UINT regno, SI newval) +{ + CPU (h_asr[regno]) = newval; +} + +/* Get the value of h-annul-p. */ + +BI +sparc64_h_annul_p_get (SIM_CPU *current_cpu) +{ + return CPU (h_annul_p); +} + +/* Set a value for h-annul-p. */ + +void +sparc64_h_annul_p_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_annul_p) = newval; +} + +/* Get the value of h-fr. */ + +SF +sparc64_h_fr_get (SIM_CPU *current_cpu, UINT regno) +{ + return CPU (h_fr[regno]); +} + +/* Set a value for h-fr. */ + +void +sparc64_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval) +{ + CPU (h_fr[regno]) = newval; +} + +/* Get the value of h-ver. */ + +UDI +sparc64_h_ver_get (SIM_CPU *current_cpu) +{ + return CPU (h_ver); +} + +/* Set a value for h-ver. */ + +void +sparc64_h_ver_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_ver) = newval; +} + +/* Get the value of h-pstate. */ + +UDI +sparc64_h_pstate_get (SIM_CPU *current_cpu) +{ + return CPU (h_pstate); +} + +/* Set a value for h-pstate. */ + +void +sparc64_h_pstate_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_pstate) = newval; +} + +/* Get the value of h-tba. */ + +UDI +sparc64_h_tba_get (SIM_CPU *current_cpu) +{ + return CPU (h_tba); +} + +/* Set a value for h-tba. */ + +void +sparc64_h_tba_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_tba) = newval; +} + +/* Get the value of h-tt. */ + +UDI +sparc64_h_tt_get (SIM_CPU *current_cpu) +{ + return CPU (h_tt); +} + +/* Set a value for h-tt. */ + +void +sparc64_h_tt_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_tt) = newval; +} + +/* Get the value of h-tpc. */ + +UDI +sparc64_h_tpc_get (SIM_CPU *current_cpu) +{ + return CPU (h_tpc); +} + +/* Set a value for h-tpc. */ + +void +sparc64_h_tpc_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_tpc) = newval; +} + +/* Get the value of h-tnpc. */ + +UDI +sparc64_h_tnpc_get (SIM_CPU *current_cpu) +{ + return CPU (h_tnpc); +} + +/* Set a value for h-tnpc. */ + +void +sparc64_h_tnpc_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_tnpc) = newval; +} + +/* Get the value of h-tstate. */ + +UDI +sparc64_h_tstate_get (SIM_CPU *current_cpu) +{ + return CPU (h_tstate); +} + +/* Set a value for h-tstate. */ + +void +sparc64_h_tstate_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_tstate) = newval; +} + +/* Get the value of h-tl. */ + +UQI +sparc64_h_tl_get (SIM_CPU *current_cpu) +{ + return CPU (h_tl); +} + +/* Set a value for h-tl. */ + +void +sparc64_h_tl_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_tl) = newval; +} + +/* Get the value of h-asi. */ + +UQI +sparc64_h_asi_get (SIM_CPU *current_cpu) +{ + return CPU (h_asi); +} + +/* Set a value for h-asi. */ + +void +sparc64_h_asi_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_asi) = newval; +} + +/* Get the value of h-tick. */ + +UDI +sparc64_h_tick_get (SIM_CPU *current_cpu) +{ + return CPU (h_tick); +} + +/* Set a value for h-tick. */ + +void +sparc64_h_tick_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_tick) = newval; +} + +/* Get the value of h-cansave. */ + +UDI +sparc64_h_cansave_get (SIM_CPU *current_cpu) +{ + return CPU (h_cansave); +} + +/* Set a value for h-cansave. */ + +void +sparc64_h_cansave_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_cansave) = newval; +} + +/* Get the value of h-canrestore. */ + +UDI +sparc64_h_canrestore_get (SIM_CPU *current_cpu) +{ + return CPU (h_canrestore); +} + +/* Set a value for h-canrestore. */ + +void +sparc64_h_canrestore_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_canrestore) = newval; +} + +/* Get the value of h-otherwin. */ + +UDI +sparc64_h_otherwin_get (SIM_CPU *current_cpu) +{ + return CPU (h_otherwin); +} + +/* Set a value for h-otherwin. */ + +void +sparc64_h_otherwin_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_otherwin) = newval; +} + +/* Get the value of h-cleanwin. */ + +UDI +sparc64_h_cleanwin_get (SIM_CPU *current_cpu) +{ + return CPU (h_cleanwin); +} + +/* Set a value for h-cleanwin. */ + +void +sparc64_h_cleanwin_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_cleanwin) = newval; +} + +/* Get the value of h-wstate. */ + +UDI +sparc64_h_wstate_get (SIM_CPU *current_cpu) +{ + return CPU (h_wstate); +} + +/* Set a value for h-wstate. */ + +void +sparc64_h_wstate_set (SIM_CPU *current_cpu, UDI newval) +{ + CPU (h_wstate) = newval; +} + +/* Get the value of h-fcc0. */ + +UQI +sparc64_h_fcc0_get (SIM_CPU *current_cpu) +{ + return CPU (h_fcc0); +} + +/* Set a value for h-fcc0. */ + +void +sparc64_h_fcc0_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_fcc0) = newval; +} + +/* Get the value of h-fcc1. */ + +UQI +sparc64_h_fcc1_get (SIM_CPU *current_cpu) +{ + return CPU (h_fcc1); +} + +/* Set a value for h-fcc1. */ + +void +sparc64_h_fcc1_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_fcc1) = newval; +} + +/* Get the value of h-fcc2. */ + +UQI +sparc64_h_fcc2_get (SIM_CPU *current_cpu) +{ + return CPU (h_fcc2); +} + +/* Set a value for h-fcc2. */ + +void +sparc64_h_fcc2_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_fcc2) = newval; +} + +/* Get the value of h-fcc3. */ + +UQI +sparc64_h_fcc3_get (SIM_CPU *current_cpu) +{ + return CPU (h_fcc3); +} + +/* Set a value for h-fcc3. */ + +void +sparc64_h_fcc3_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_fcc3) = newval; +} + +/* Get the value of h-fsr-rd. */ + +UQI +sparc64_h_fsr_rd_get (SIM_CPU *current_cpu) +{ + return CPU (h_fsr_rd); +} + +/* Set a value for h-fsr-rd. */ + +void +sparc64_h_fsr_rd_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_fsr_rd) = newval; +} + +/* Get the value of h-fsr-tem. */ + +UQI +sparc64_h_fsr_tem_get (SIM_CPU *current_cpu) +{ + return CPU (h_fsr_tem); +} + +/* Set a value for h-fsr-tem. */ + +void +sparc64_h_fsr_tem_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_fsr_tem) = newval; +} + +/* Get the value of h-fsr-ns. */ + +BI +sparc64_h_fsr_ns_get (SIM_CPU *current_cpu) +{ + return CPU (h_fsr_ns); +} + +/* Set a value for h-fsr-ns. */ + +void +sparc64_h_fsr_ns_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_fsr_ns) = newval; +} + +/* Get the value of h-fsr-ver. */ + +UQI +sparc64_h_fsr_ver_get (SIM_CPU *current_cpu) +{ + return CPU (h_fsr_ver); +} + +/* Set a value for h-fsr-ver. */ + +void +sparc64_h_fsr_ver_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_fsr_ver) = newval; +} + +/* Get the value of h-fsr-ftt. */ + +UQI +sparc64_h_fsr_ftt_get (SIM_CPU *current_cpu) +{ + return CPU (h_fsr_ftt); +} + +/* Set a value for h-fsr-ftt. */ + +void +sparc64_h_fsr_ftt_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_fsr_ftt) = newval; +} + +/* Get the value of h-fsr-qne. */ + +BI +sparc64_h_fsr_qne_get (SIM_CPU *current_cpu) +{ + return CPU (h_fsr_qne); +} + +/* Set a value for h-fsr-qne. */ + +void +sparc64_h_fsr_qne_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_fsr_qne) = newval; +} + +/* Get the value of h-fsr-aexc. */ + +UQI +sparc64_h_fsr_aexc_get (SIM_CPU *current_cpu) +{ + return CPU (h_fsr_aexc); +} + +/* Set a value for h-fsr-aexc. */ + +void +sparc64_h_fsr_aexc_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_fsr_aexc) = newval; +} + +/* Get the value of h-fsr-cexc. */ + +UQI +sparc64_h_fsr_cexc_get (SIM_CPU *current_cpu) +{ + return CPU (h_fsr_cexc); +} + +/* Set a value for h-fsr-cexc. */ + +void +sparc64_h_fsr_cexc_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_fsr_cexc) = newval; +} + +/* Get the value of h-fpsr-fef. */ + +BI +sparc64_h_fpsr_fef_get (SIM_CPU *current_cpu) +{ + return CPU (h_fpsr_fef); +} + +/* Set a value for h-fpsr-fef. */ + +void +sparc64_h_fpsr_fef_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_fpsr_fef) = newval; +} + +/* Get the value of h-fpsr-du. */ + +BI +sparc64_h_fpsr_du_get (SIM_CPU *current_cpu) +{ + return CPU (h_fpsr_du); +} + +/* Set a value for h-fpsr-du. */ + +void +sparc64_h_fpsr_du_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_fpsr_du) = newval; +} + +/* Get the value of h-fpsr-dl. */ + +BI +sparc64_h_fpsr_dl_get (SIM_CPU *current_cpu) +{ + return CPU (h_fpsr_dl); +} + +/* Set a value for h-fpsr-dl. */ + +void +sparc64_h_fpsr_dl_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_fpsr_dl) = newval; +} + +/* Get the value of h-fpsr. */ + +UQI +sparc64_h_fpsr_get (SIM_CPU *current_cpu) +{ + return GET_H_FPSR (); +} + +/* Set a value for h-fpsr. */ + +void +sparc64_h_fpsr_set (SIM_CPU *current_cpu, UQI newval) +{ + SET_H_FPSR (newval); +} + +/* Record trace results for INSN. */ + +void +sparc64_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn, + int *indices, TRACE_RECORD *tr) +{ +} diff --git a/sim/sparc/cpu64.h b/sim/sparc/cpu64.h new file mode 100644 index 0000000000..1a6e4a917c --- /dev/null +++ b/sim/sparc/cpu64.h @@ -0,0 +1,818 @@ +/* CPU family header for sparc64. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#ifndef CPU_SPARC64_H +#define CPU_SPARC64_H + +/* Maximum number of instructions that are fetched at a time. + This is for LIW type instructions sets (e.g. m32r). */ +#define MAX_LIW_INSNS 1 + +/* Maximum number of instructions that can be executed in parallel. */ +#define MAX_PARALLEL_INSNS 1 + +/* CPU state information. */ +typedef struct { + /* Hardware elements. */ + struct { + /* program counter */ + USI h_pc; +#define GET_H_PC() CPU (h_pc) +#define SET_H_PC(x) (CPU (h_pc) = (x)) + /* next pc */ + SI h_npc; +#define GET_H_NPC() CPU (h_npc) +#define SET_H_NPC(x) (CPU (h_npc) = (x)) +/* GET_H_GR macro user-written */ +/* SET_H_GR macro user-written */ + /* icc carry bit */ + BI h_icc_c; +#define GET_H_ICC_C() CPU (h_icc_c) +#define SET_H_ICC_C(x) (CPU (h_icc_c) = (x)) + /* icc negative bit */ + BI h_icc_n; +#define GET_H_ICC_N() CPU (h_icc_n) +#define SET_H_ICC_N(x) (CPU (h_icc_n) = (x)) + /* icc overflow bit */ + BI h_icc_v; +#define GET_H_ICC_V() CPU (h_icc_v) +#define SET_H_ICC_V(x) (CPU (h_icc_v) = (x)) + /* icc zero bit */ + BI h_icc_z; +#define GET_H_ICC_Z() CPU (h_icc_z) +#define SET_H_ICC_Z(x) (CPU (h_icc_z) = (x)) + /* xcc carry bit */ + BI h_xcc_c; +#define GET_H_XCC_C() CPU (h_xcc_c) +#define SET_H_XCC_C(x) (CPU (h_xcc_c) = (x)) + /* xcc negative bit */ + BI h_xcc_n; +#define GET_H_XCC_N() CPU (h_xcc_n) +#define SET_H_XCC_N(x) (CPU (h_xcc_n) = (x)) + /* xcc overflow bit */ + BI h_xcc_v; +#define GET_H_XCC_V() CPU (h_xcc_v) +#define SET_H_XCC_V(x) (CPU (h_xcc_v) = (x)) + /* xcc zero bit */ + BI h_xcc_z; +#define GET_H_XCC_Z() CPU (h_xcc_z) +#define SET_H_XCC_Z(x) (CPU (h_xcc_z) = (x)) +/* GET_H_Y macro user-written */ +/* SET_H_Y macro user-written */ + /* ancilliary state registers */ + SI h_asr[32]; +#define GET_H_ASR(a1) CPU (h_asr)[a1] +#define SET_H_ASR(a1, x) (CPU (h_asr)[a1] = (x)) + /* annul next insn? - assists execution */ + BI h_annul_p; +#define GET_H_ANNUL_P() CPU (h_annul_p) +#define SET_H_ANNUL_P(x) (CPU (h_annul_p) = (x)) + /* floating point regs */ + SF h_fr[32]; +#define GET_H_FR(a1) CPU (h_fr)[a1] +#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x)) + /* version */ + UDI h_ver; +#define GET_H_VER() CPU (h_ver) +#define SET_H_VER(x) (CPU (h_ver) = (x)) + /* processor state */ + UDI h_pstate; +#define GET_H_PSTATE() CPU (h_pstate) +#define SET_H_PSTATE(x) (CPU (h_pstate) = (x)) + /* trap base address */ + UDI h_tba; +#define GET_H_TBA() CPU (h_tba) +#define SET_H_TBA(x) (CPU (h_tba) = (x)) + /* trap type */ + UDI h_tt; +#define GET_H_TT() CPU (h_tt) +#define SET_H_TT(x) (CPU (h_tt) = (x)) + /* trap pc */ + UDI h_tpc; +#define GET_H_TPC() CPU (h_tpc) +#define SET_H_TPC(x) (CPU (h_tpc) = (x)) + /* trap npc */ + UDI h_tnpc; +#define GET_H_TNPC() CPU (h_tnpc) +#define SET_H_TNPC(x) (CPU (h_tnpc) = (x)) + /* trap state */ + UDI h_tstate; +#define GET_H_TSTATE() CPU (h_tstate) +#define SET_H_TSTATE(x) (CPU (h_tstate) = (x)) + /* trap level */ + UQI h_tl; +#define GET_H_TL() CPU (h_tl) +#define SET_H_TL(x) (CPU (h_tl) = (x)) + /* address space identifier */ + UQI h_asi; +#define GET_H_ASI() CPU (h_asi) +#define SET_H_ASI(x) (CPU (h_asi) = (x)) + /* tick counter */ + UDI h_tick; +#define GET_H_TICK() CPU (h_tick) +#define SET_H_TICK(x) (CPU (h_tick) = (x)) + /* savable window registers */ + UDI h_cansave; +#define GET_H_CANSAVE() CPU (h_cansave) +#define SET_H_CANSAVE(x) (CPU (h_cansave) = (x)) + /* restorable window registers */ + UDI h_canrestore; +#define GET_H_CANRESTORE() CPU (h_canrestore) +#define SET_H_CANRESTORE(x) (CPU (h_canrestore) = (x)) + /* other window registers */ + UDI h_otherwin; +#define GET_H_OTHERWIN() CPU (h_otherwin) +#define SET_H_OTHERWIN(x) (CPU (h_otherwin) = (x)) + /* clean window registers */ + UDI h_cleanwin; +#define GET_H_CLEANWIN() CPU (h_cleanwin) +#define SET_H_CLEANWIN(x) (CPU (h_cleanwin) = (x)) + /* window state */ + UDI h_wstate; +#define GET_H_WSTATE() CPU (h_wstate) +#define SET_H_WSTATE(x) (CPU (h_wstate) = (x)) + /* */ + UQI h_fcc0; +#define GET_H_FCC0() CPU (h_fcc0) +#define SET_H_FCC0(x) (CPU (h_fcc0) = (x)) + /* */ + UQI h_fcc1; +#define GET_H_FCC1() CPU (h_fcc1) +#define SET_H_FCC1(x) (CPU (h_fcc1) = (x)) + /* */ + UQI h_fcc2; +#define GET_H_FCC2() CPU (h_fcc2) +#define SET_H_FCC2(x) (CPU (h_fcc2) = (x)) + /* */ + UQI h_fcc3; +#define GET_H_FCC3() CPU (h_fcc3) +#define SET_H_FCC3(x) (CPU (h_fcc3) = (x)) + /* fsr rounding direction */ + UQI h_fsr_rd; +#define GET_H_FSR_RD() CPU (h_fsr_rd) +#define SET_H_FSR_RD(x) (CPU (h_fsr_rd) = (x)) + /* fsr trap enable mask */ + UQI h_fsr_tem; +#define GET_H_FSR_TEM() CPU (h_fsr_tem) +#define SET_H_FSR_TEM(x) (CPU (h_fsr_tem) = (x)) + /* fsr nonstandard fp */ + BI h_fsr_ns; +#define GET_H_FSR_NS() CPU (h_fsr_ns) +#define SET_H_FSR_NS(x) (CPU (h_fsr_ns) = (x)) + /* fsr version */ + UQI h_fsr_ver; +#define GET_H_FSR_VER() CPU (h_fsr_ver) +#define SET_H_FSR_VER(x) (CPU (h_fsr_ver) = (x)) + /* fsr fp trap type */ + UQI h_fsr_ftt; +#define GET_H_FSR_FTT() CPU (h_fsr_ftt) +#define SET_H_FSR_FTT(x) (CPU (h_fsr_ftt) = (x)) + /* fsr queue not empty */ + BI h_fsr_qne; +#define GET_H_FSR_QNE() CPU (h_fsr_qne) +#define SET_H_FSR_QNE(x) (CPU (h_fsr_qne) = (x)) + /* fsr accrued exception */ + UQI h_fsr_aexc; +#define GET_H_FSR_AEXC() CPU (h_fsr_aexc) +#define SET_H_FSR_AEXC(x) (CPU (h_fsr_aexc) = (x)) + /* fsr current exception */ + UQI h_fsr_cexc; +#define GET_H_FSR_CEXC() CPU (h_fsr_cexc) +#define SET_H_FSR_CEXC(x) (CPU (h_fsr_cexc) = (x)) + /* fpsr enable fp */ + BI h_fpsr_fef; +#define GET_H_FPSR_FEF() CPU (h_fpsr_fef) +#define SET_H_FPSR_FEF(x) (CPU (h_fpsr_fef) = (x)) + /* fpsr dirty upper */ + BI h_fpsr_du; +#define GET_H_FPSR_DU() CPU (h_fpsr_du) +#define SET_H_FPSR_DU(x) (CPU (h_fpsr_du) = (x)) + /* fpsr dirty lower */ + BI h_fpsr_dl; +#define GET_H_FPSR_DL() CPU (h_fpsr_dl) +#define SET_H_FPSR_DL(x) (CPU (h_fpsr_dl) = (x)) +/* GET_H_FPSR macro user-written */ +/* SET_H_FPSR macro user-written */ + } hardware; +#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) +} SPARC64_CPU_DATA; + +/* Cover fns for register access. */ +USI sparc64_h_pc_get (SIM_CPU *); +void sparc64_h_pc_set (SIM_CPU *, USI); +SI sparc64_h_npc_get (SIM_CPU *); +void sparc64_h_npc_set (SIM_CPU *, SI); +SI sparc64_h_gr_get (SIM_CPU *, UINT); +void sparc64_h_gr_set (SIM_CPU *, UINT, SI); +BI sparc64_h_icc_c_get (SIM_CPU *); +void sparc64_h_icc_c_set (SIM_CPU *, BI); +BI sparc64_h_icc_n_get (SIM_CPU *); +void sparc64_h_icc_n_set (SIM_CPU *, BI); +BI sparc64_h_icc_v_get (SIM_CPU *); +void sparc64_h_icc_v_set (SIM_CPU *, BI); +BI sparc64_h_icc_z_get (SIM_CPU *); +void sparc64_h_icc_z_set (SIM_CPU *, BI); +BI sparc64_h_xcc_c_get (SIM_CPU *); +void sparc64_h_xcc_c_set (SIM_CPU *, BI); +BI sparc64_h_xcc_n_get (SIM_CPU *); +void sparc64_h_xcc_n_set (SIM_CPU *, BI); +BI sparc64_h_xcc_v_get (SIM_CPU *); +void sparc64_h_xcc_v_set (SIM_CPU *, BI); +BI sparc64_h_xcc_z_get (SIM_CPU *); +void sparc64_h_xcc_z_set (SIM_CPU *, BI); +SI sparc64_h_y_get (SIM_CPU *); +void sparc64_h_y_set (SIM_CPU *, SI); +SI sparc64_h_asr_get (SIM_CPU *, UINT); +void sparc64_h_asr_set (SIM_CPU *, UINT, SI); +BI sparc64_h_annul_p_get (SIM_CPU *); +void sparc64_h_annul_p_set (SIM_CPU *, BI); +SF sparc64_h_fr_get (SIM_CPU *, UINT); +void sparc64_h_fr_set (SIM_CPU *, UINT, SF); +UDI sparc64_h_ver_get (SIM_CPU *); +void sparc64_h_ver_set (SIM_CPU *, UDI); +UDI sparc64_h_pstate_get (SIM_CPU *); +void sparc64_h_pstate_set (SIM_CPU *, UDI); +UDI sparc64_h_tba_get (SIM_CPU *); +void sparc64_h_tba_set (SIM_CPU *, UDI); +UDI sparc64_h_tt_get (SIM_CPU *); +void sparc64_h_tt_set (SIM_CPU *, UDI); +UDI sparc64_h_tpc_get (SIM_CPU *); +void sparc64_h_tpc_set (SIM_CPU *, UDI); +UDI sparc64_h_tnpc_get (SIM_CPU *); +void sparc64_h_tnpc_set (SIM_CPU *, UDI); +UDI sparc64_h_tstate_get (SIM_CPU *); +void sparc64_h_tstate_set (SIM_CPU *, UDI); +UQI sparc64_h_tl_get (SIM_CPU *); +void sparc64_h_tl_set (SIM_CPU *, UQI); +UQI sparc64_h_asi_get (SIM_CPU *); +void sparc64_h_asi_set (SIM_CPU *, UQI); +UDI sparc64_h_tick_get (SIM_CPU *); +void sparc64_h_tick_set (SIM_CPU *, UDI); +UDI sparc64_h_cansave_get (SIM_CPU *); +void sparc64_h_cansave_set (SIM_CPU *, UDI); +UDI sparc64_h_canrestore_get (SIM_CPU *); +void sparc64_h_canrestore_set (SIM_CPU *, UDI); +UDI sparc64_h_otherwin_get (SIM_CPU *); +void sparc64_h_otherwin_set (SIM_CPU *, UDI); +UDI sparc64_h_cleanwin_get (SIM_CPU *); +void sparc64_h_cleanwin_set (SIM_CPU *, UDI); +UDI sparc64_h_wstate_get (SIM_CPU *); +void sparc64_h_wstate_set (SIM_CPU *, UDI); +UQI sparc64_h_fcc0_get (SIM_CPU *); +void sparc64_h_fcc0_set (SIM_CPU *, UQI); +UQI sparc64_h_fcc1_get (SIM_CPU *); +void sparc64_h_fcc1_set (SIM_CPU *, UQI); +UQI sparc64_h_fcc2_get (SIM_CPU *); +void sparc64_h_fcc2_set (SIM_CPU *, UQI); +UQI sparc64_h_fcc3_get (SIM_CPU *); +void sparc64_h_fcc3_set (SIM_CPU *, UQI); +UQI sparc64_h_fsr_rd_get (SIM_CPU *); +void sparc64_h_fsr_rd_set (SIM_CPU *, UQI); +UQI sparc64_h_fsr_tem_get (SIM_CPU *); +void sparc64_h_fsr_tem_set (SIM_CPU *, UQI); +BI sparc64_h_fsr_ns_get (SIM_CPU *); +void sparc64_h_fsr_ns_set (SIM_CPU *, BI); +UQI sparc64_h_fsr_ver_get (SIM_CPU *); +void sparc64_h_fsr_ver_set (SIM_CPU *, UQI); +UQI sparc64_h_fsr_ftt_get (SIM_CPU *); +void sparc64_h_fsr_ftt_set (SIM_CPU *, UQI); +BI sparc64_h_fsr_qne_get (SIM_CPU *); +void sparc64_h_fsr_qne_set (SIM_CPU *, BI); +UQI sparc64_h_fsr_aexc_get (SIM_CPU *); +void sparc64_h_fsr_aexc_set (SIM_CPU *, UQI); +UQI sparc64_h_fsr_cexc_get (SIM_CPU *); +void sparc64_h_fsr_cexc_set (SIM_CPU *, UQI); +BI sparc64_h_fpsr_fef_get (SIM_CPU *); +void sparc64_h_fpsr_fef_set (SIM_CPU *, BI); +BI sparc64_h_fpsr_du_get (SIM_CPU *); +void sparc64_h_fpsr_du_set (SIM_CPU *, BI); +BI sparc64_h_fpsr_dl_get (SIM_CPU *); +void sparc64_h_fpsr_dl_set (SIM_CPU *, BI); +UQI sparc64_h_fpsr_get (SIM_CPU *); +void sparc64_h_fpsr_set (SIM_CPU *, UQI); + +/* These must be hand-written. */ +extern CPUREG_FETCH_FN sparc64_fetch_register; +extern CPUREG_STORE_FN sparc64_store_register; + +typedef struct { + int empty; +} MODEL_SPARC64_DEF_DATA; + +/* The ARGBUF struct. */ +struct argbuf { + /* These are the baseclass definitions. */ + IADDR addr; + const IDESC *idesc; + char trace_p; + char profile_p; + /* cpu specific data follows */ + CGEN_INSN_INT insn; + int written; +}; + +/* A cached insn. + + ??? SCACHE used to contain more than just argbuf. We could delete the + type entirely and always just use ARGBUF, but for future concerns and as + a level of abstraction it is left in. */ + +struct scache { + struct argbuf argbuf; +}; + +/* Macros to simplify extraction, reading and semantic code. + These define and assign the local vars that contain the insn's fields. */ + +#define EXTRACT_IFMT_EMPTY_VARS \ + /* Instruction fields. */ \ + unsigned int length; +#define EXTRACT_IFMT_EMPTY_CODE \ + length = 0; \ + +#define EXTRACT_IFMT_BEQZ_VARS \ + /* Instruction fields. */ \ + INT f_disp16; \ + UINT f_disp16_hi; \ + UINT f_disp16_lo; \ + UINT f_rs1; \ + UINT f_p; \ + UINT f_op2; \ + UINT f_fmt2_rcond; \ + INT f_bpr_res28_1; \ + UINT f_a; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_BEQZ_CODE \ + length = 4; \ + f_disp16_hi = EXTRACT_UINT (insn, 32, 10, 2); \ + f_disp16_lo = EXTRACT_UINT (insn, 32, 18, 14); \ +do {\ + f_disp16 = ((((f_disp16_hi) << (14))) | (f_disp16_low));\ +} while (0);\ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_p = EXTRACT_UINT (insn, 32, 19, 1); \ + f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ + f_fmt2_rcond = EXTRACT_UINT (insn, 32, 27, 3); \ + f_bpr_res28_1 = EXTRACT_INT (insn, 32, 28, 1); \ + f_a = EXTRACT_UINT (insn, 32, 29, 1); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_BPCC_BA_VARS \ + /* Instruction fields. */ \ + INT f_disp19; \ + UINT f_p; \ + UINT f_fmt2_cc0; \ + UINT f_fmt2_cc1; \ + UINT f_op2; \ + UINT f_fmt2_cond; \ + UINT f_a; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_BPCC_BA_CODE \ + length = 4; \ + f_disp19 = EXTRACT_INT (insn, 32, 13, 19); \ + f_p = EXTRACT_UINT (insn, 32, 19, 1); \ + f_fmt2_cc0 = EXTRACT_UINT (insn, 32, 20, 1); \ + f_fmt2_cc1 = EXTRACT_UINT (insn, 32, 21, 1); \ + f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ + f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ + f_a = EXTRACT_UINT (insn, 32, 29, 1); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_DONE_VARS \ + /* Instruction fields. */ \ + INT f_res_18_19; \ + UINT f_op3; \ + UINT f_fcn; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_DONE_CODE \ + length = 4; \ + f_res_18_19 = EXTRACT_INT (insn, 32, 18, 19); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_fcn = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_FLUSH_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_res_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_FLUSH_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_FLUSH_IMM_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_FLUSH_IMM_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_FLUSHW_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_FLUSHW_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_IMPDEP1_VARS \ + /* Instruction fields. */ \ + INT f_impdep19; \ + UINT f_op3; \ + INT f_impdep5; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_IMPDEP1_CODE \ + length = 4; \ + f_impdep19 = EXTRACT_INT (insn, 32, 18, 19); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_impdep5 = EXTRACT_INT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_MEMBAR_VARS \ + /* Instruction fields. */ \ + UINT f_membarmask; \ + INT f_membar_res12_6; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_MEMBAR_CODE \ + length = 4; \ + f_membarmask = EXTRACT_UINT (insn, 32, 6, 7); \ + f_membar_res12_6 = EXTRACT_INT (insn, 32, 12, 6); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_MOVA_ICC_ICC_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_fmt4_res10_6; \ + UINT f_fmt4_cc1_0; \ + UINT f_i; \ + UINT f_fmt4_cc2; \ + UINT f_op3; \ + UINT f_fmt2_cond; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_MOVA_ICC_ICC_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_fmt4_res10_6 = EXTRACT_INT (insn, 32, 10, 6); \ + f_fmt4_cc1_0 = EXTRACT_UINT (insn, 32, 12, 2); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_fmt4_cc2 = EXTRACT_UINT (insn, 32, 18, 1); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS \ + /* Instruction fields. */ \ + INT f_simm11; \ + UINT f_fmt4_cc1_0; \ + UINT f_i; \ + UINT f_fmt4_cc2; \ + UINT f_op3; \ + UINT f_fmt2_cond; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE \ + length = 4; \ + f_simm11 = EXTRACT_INT (insn, 32, 10, 11); \ + f_fmt4_cc1_0 = EXTRACT_UINT (insn, 32, 12, 2); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_fmt4_cc2 = EXTRACT_UINT (insn, 32, 18, 1); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDSB_REG_REG_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_res_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDSB_REG_REG_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDSB_REG_IMM_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDSB_REG_IMM_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + UINT f_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDD_REG_REG_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_res_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDD_REG_REG_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDD_REG_IMM_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDD_REG_IMM_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDD_REG_REG_ASI_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + UINT f_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDD_REG_REG_ASI_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_FP_LD_REG_REG_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_res_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_FP_LD_REG_REG_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_FP_LD_REG_IMM_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_FP_LD_REG_IMM_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + UINT f_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_SETHI_VARS \ + /* Instruction fields. */ \ + INT f_hi22; \ + UINT f_op2; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_SETHI_CODE \ + length = 4; \ + f_hi22 = EXTRACT_INT (insn, 32, 21, 22); \ + f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_UNIMP_VARS \ + /* Instruction fields. */ \ + INT f_imm22; \ + UINT f_op2; \ + UINT f_rd_res; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_UNIMP_CODE \ + length = 4; \ + f_imm22 = EXTRACT_INT (insn, 32, 21, 22); \ + f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ + f_rd_res = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_CALL_VARS \ + /* Instruction fields. */ \ + SI f_disp30; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_CALL_CODE \ + length = 4; \ + f_disp30 = ((((EXTRACT_INT (insn, 32, 29, 30)) << (2))) + (pc)); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_BA_VARS \ + /* Instruction fields. */ \ + SI f_disp22; \ + UINT f_op2; \ + UINT f_fmt2_cond; \ + UINT f_a; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_BA_CODE \ + length = 4; \ + f_disp22 = ((((EXTRACT_INT (insn, 32, 21, 22)) << (2))) + (pc)); \ + f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ + f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ + f_a = EXTRACT_UINT (insn, 32, 29, 1); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_TA_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_res_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_fmt2_cond; \ + UINT f_a; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_TA_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ + f_a = EXTRACT_UINT (insn, 32, 29, 1); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_TA_IMM_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_fmt2_cond; \ + UINT f_a; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_TA_IMM_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ + f_a = EXTRACT_UINT (insn, 32, 29, 1); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +/* Collection of various things for the trace handler to use. */ + +typedef struct trace_record { + IADDR pc; + /* FIXME:wip */ +} TRACE_RECORD; + +#endif /* CPU_SPARC64_H */ diff --git a/sim/sparc/decode64.c b/sim/sparc/decode64.c new file mode 100644 index 0000000000..ed5eb06bce --- /dev/null +++ b/sim/sparc/decode64.c @@ -0,0 +1,1602 @@ +/* Simulator instruction decoder for sparc64. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#define WANT_CPU sparc64 +#define WANT_CPU_SPARC64 + +#include "sim-main.h" +#include "sim-assert.h" + +/* FIXME: Need to review choices for the following. */ + +#if WITH_SEM_SWITCH_FULL +#define FULL(fn) +#else +#define FULL(fn) CONCAT3 (sparc64,_sem_,fn) , +#endif + +#if WITH_FAST +#if WITH_SEM_SWITCH_FAST +#define FAST(fn) +#else +#define FAST(fn) CONCAT3 (sparc64,_semf_,fn) , /* f for fast */ +#endif +#else +#define FAST(fn) +#endif + +/* The instruction descriptor array. + This is computed at runtime. Space for it is not malloc'd to save a + teensy bit of cpu in the decoder. Moving it to malloc space is trivial + but won't be done until necessary (we don't currently support the runtime + addition of instructions nor an SMP machine with different cpus). */ +static IDESC sparc64_insn_data[SPARC64_INSN_MAX]; + +/* The INSN_ prefix is not here and is instead part of the `insn' argument + to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ +#define IDX(insn) CONCAT2 (SPARC64_,insn) +#define TYPE(insn) CONCAT2 (SPARC_,insn) + +/* Commas between elements are contained in the macros. + Some of these are conditionally compiled out. */ + +static const struct insn_sem sparc64_insn_sem[] = +{ + { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }, + { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) }, + { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) }, + { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) }, + { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) }, + { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) }, + { TYPE (INSN_BEQZ), IDX (INSN_BEQZ), FULL (beqz) FAST (beqz) }, + { TYPE (INSN_BGEZ), IDX (INSN_BGEZ), FULL (bgez) FAST (bgez) }, + { TYPE (INSN_BGTZ), IDX (INSN_BGTZ), FULL (bgtz) FAST (bgtz) }, + { TYPE (INSN_BLEZ), IDX (INSN_BLEZ), FULL (blez) FAST (blez) }, + { TYPE (INSN_BLTZ), IDX (INSN_BLTZ), FULL (bltz) FAST (bltz) }, + { TYPE (INSN_BNEZ), IDX (INSN_BNEZ), FULL (bnez) FAST (bnez) }, + { TYPE (INSN_BPCC_BA), IDX (INSN_BPCC_BA), FULL (bpcc_ba) FAST (bpcc_ba) }, + { TYPE (INSN_BPCC_BN), IDX (INSN_BPCC_BN), FULL (bpcc_bn) FAST (bpcc_bn) }, + { TYPE (INSN_BPCC_BNE), IDX (INSN_BPCC_BNE), FULL (bpcc_bne) FAST (bpcc_bne) }, + { TYPE (INSN_BPCC_BE), IDX (INSN_BPCC_BE), FULL (bpcc_be) FAST (bpcc_be) }, + { TYPE (INSN_BPCC_BG), IDX (INSN_BPCC_BG), FULL (bpcc_bg) FAST (bpcc_bg) }, + { TYPE (INSN_BPCC_BLE), IDX (INSN_BPCC_BLE), FULL (bpcc_ble) FAST (bpcc_ble) }, + { TYPE (INSN_BPCC_BGE), IDX (INSN_BPCC_BGE), FULL (bpcc_bge) FAST (bpcc_bge) }, + { TYPE (INSN_BPCC_BL), IDX (INSN_BPCC_BL), FULL (bpcc_bl) FAST (bpcc_bl) }, + { TYPE (INSN_BPCC_BGU), IDX (INSN_BPCC_BGU), FULL (bpcc_bgu) FAST (bpcc_bgu) }, + { TYPE (INSN_BPCC_BLEU), IDX (INSN_BPCC_BLEU), FULL (bpcc_bleu) FAST (bpcc_bleu) }, + { TYPE (INSN_BPCC_BCC), IDX (INSN_BPCC_BCC), FULL (bpcc_bcc) FAST (bpcc_bcc) }, + { TYPE (INSN_BPCC_BCS), IDX (INSN_BPCC_BCS), FULL (bpcc_bcs) FAST (bpcc_bcs) }, + { TYPE (INSN_BPCC_BPOS), IDX (INSN_BPCC_BPOS), FULL (bpcc_bpos) FAST (bpcc_bpos) }, + { TYPE (INSN_BPCC_BNEG), IDX (INSN_BPCC_BNEG), FULL (bpcc_bneg) FAST (bpcc_bneg) }, + { TYPE (INSN_BPCC_BVC), IDX (INSN_BPCC_BVC), FULL (bpcc_bvc) FAST (bpcc_bvc) }, + { TYPE (INSN_BPCC_BVS), IDX (INSN_BPCC_BVS), FULL (bpcc_bvs) FAST (bpcc_bvs) }, + { TYPE (INSN_DONE), IDX (INSN_DONE), FULL (done) FAST (done) }, + { TYPE (INSN_RETRY), IDX (INSN_RETRY), FULL (retry) FAST (retry) }, + { TYPE (INSN_FLUSH), IDX (INSN_FLUSH), FULL (flush) FAST (flush) }, + { TYPE (INSN_FLUSH_IMM), IDX (INSN_FLUSH_IMM), FULL (flush_imm) FAST (flush_imm) }, + { TYPE (INSN_FLUSHW), IDX (INSN_FLUSHW), FULL (flushw) FAST (flushw) }, + { TYPE (INSN_IMPDEP1), IDX (INSN_IMPDEP1), FULL (impdep1) FAST (impdep1) }, + { TYPE (INSN_IMPDEP2), IDX (INSN_IMPDEP2), FULL (impdep2) FAST (impdep2) }, + { TYPE (INSN_MEMBAR), IDX (INSN_MEMBAR), FULL (membar) FAST (membar) }, + { TYPE (INSN_MOVA_ICC_ICC), IDX (INSN_MOVA_ICC_ICC), FULL (mova_icc_icc) FAST (mova_icc_icc) }, + { TYPE (INSN_MOVA_IMM_ICC_ICC), IDX (INSN_MOVA_IMM_ICC_ICC), FULL (mova_imm_icc_icc) FAST (mova_imm_icc_icc) }, + { TYPE (INSN_MOVA_XCC_XCC), IDX (INSN_MOVA_XCC_XCC), FULL (mova_xcc_xcc) FAST (mova_xcc_xcc) }, + { TYPE (INSN_MOVA_IMM_XCC_XCC), IDX (INSN_MOVA_IMM_XCC_XCC), FULL (mova_imm_xcc_xcc) FAST (mova_imm_xcc_xcc) }, + { TYPE (INSN_MOVN_ICC_ICC), IDX (INSN_MOVN_ICC_ICC), FULL (movn_icc_icc) FAST (movn_icc_icc) }, + { TYPE (INSN_MOVN_IMM_ICC_ICC), IDX (INSN_MOVN_IMM_ICC_ICC), FULL (movn_imm_icc_icc) FAST (movn_imm_icc_icc) }, + { TYPE (INSN_MOVN_XCC_XCC), IDX (INSN_MOVN_XCC_XCC), FULL (movn_xcc_xcc) FAST (movn_xcc_xcc) }, + { TYPE (INSN_MOVN_IMM_XCC_XCC), IDX (INSN_MOVN_IMM_XCC_XCC), FULL (movn_imm_xcc_xcc) FAST (movn_imm_xcc_xcc) }, + { TYPE (INSN_MOVNE_ICC_ICC), IDX (INSN_MOVNE_ICC_ICC), FULL (movne_icc_icc) FAST (movne_icc_icc) }, + { TYPE (INSN_MOVNE_IMM_ICC_ICC), IDX (INSN_MOVNE_IMM_ICC_ICC), FULL (movne_imm_icc_icc) FAST (movne_imm_icc_icc) }, + { TYPE (INSN_MOVNE_XCC_XCC), IDX (INSN_MOVNE_XCC_XCC), FULL (movne_xcc_xcc) FAST (movne_xcc_xcc) }, + { TYPE (INSN_MOVNE_IMM_XCC_XCC), IDX (INSN_MOVNE_IMM_XCC_XCC), FULL (movne_imm_xcc_xcc) FAST (movne_imm_xcc_xcc) }, + { TYPE (INSN_MOVE_ICC_ICC), IDX (INSN_MOVE_ICC_ICC), FULL (move_icc_icc) FAST (move_icc_icc) }, + { TYPE (INSN_MOVE_IMM_ICC_ICC), IDX (INSN_MOVE_IMM_ICC_ICC), FULL (move_imm_icc_icc) FAST (move_imm_icc_icc) }, + { TYPE (INSN_MOVE_XCC_XCC), IDX (INSN_MOVE_XCC_XCC), FULL (move_xcc_xcc) FAST (move_xcc_xcc) }, + { TYPE (INSN_MOVE_IMM_XCC_XCC), IDX (INSN_MOVE_IMM_XCC_XCC), FULL (move_imm_xcc_xcc) FAST (move_imm_xcc_xcc) }, + { TYPE (INSN_MOVG_ICC_ICC), IDX (INSN_MOVG_ICC_ICC), FULL (movg_icc_icc) FAST (movg_icc_icc) }, + { TYPE (INSN_MOVG_IMM_ICC_ICC), IDX (INSN_MOVG_IMM_ICC_ICC), FULL (movg_imm_icc_icc) FAST (movg_imm_icc_icc) }, + { TYPE (INSN_MOVG_XCC_XCC), IDX (INSN_MOVG_XCC_XCC), FULL (movg_xcc_xcc) FAST (movg_xcc_xcc) }, + { TYPE (INSN_MOVG_IMM_XCC_XCC), IDX (INSN_MOVG_IMM_XCC_XCC), FULL (movg_imm_xcc_xcc) FAST (movg_imm_xcc_xcc) }, + { TYPE (INSN_MOVLE_ICC_ICC), IDX (INSN_MOVLE_ICC_ICC), FULL (movle_icc_icc) FAST (movle_icc_icc) }, + { TYPE (INSN_MOVLE_IMM_ICC_ICC), IDX (INSN_MOVLE_IMM_ICC_ICC), FULL (movle_imm_icc_icc) FAST (movle_imm_icc_icc) }, + { TYPE (INSN_MOVLE_XCC_XCC), IDX (INSN_MOVLE_XCC_XCC), FULL (movle_xcc_xcc) FAST (movle_xcc_xcc) }, + { TYPE (INSN_MOVLE_IMM_XCC_XCC), IDX (INSN_MOVLE_IMM_XCC_XCC), FULL (movle_imm_xcc_xcc) FAST (movle_imm_xcc_xcc) }, + { TYPE (INSN_MOVGE_ICC_ICC), IDX (INSN_MOVGE_ICC_ICC), FULL (movge_icc_icc) FAST (movge_icc_icc) }, + { TYPE (INSN_MOVGE_IMM_ICC_ICC), IDX (INSN_MOVGE_IMM_ICC_ICC), FULL (movge_imm_icc_icc) FAST (movge_imm_icc_icc) }, + { TYPE (INSN_MOVGE_XCC_XCC), IDX (INSN_MOVGE_XCC_XCC), FULL (movge_xcc_xcc) FAST (movge_xcc_xcc) }, + { TYPE (INSN_MOVGE_IMM_XCC_XCC), IDX (INSN_MOVGE_IMM_XCC_XCC), FULL (movge_imm_xcc_xcc) FAST (movge_imm_xcc_xcc) }, + { TYPE (INSN_MOVL_ICC_ICC), IDX (INSN_MOVL_ICC_ICC), FULL (movl_icc_icc) FAST (movl_icc_icc) }, + { TYPE (INSN_MOVL_IMM_ICC_ICC), IDX (INSN_MOVL_IMM_ICC_ICC), FULL (movl_imm_icc_icc) FAST (movl_imm_icc_icc) }, + { TYPE (INSN_MOVL_XCC_XCC), IDX (INSN_MOVL_XCC_XCC), FULL (movl_xcc_xcc) FAST (movl_xcc_xcc) }, + { TYPE (INSN_MOVL_IMM_XCC_XCC), IDX (INSN_MOVL_IMM_XCC_XCC), FULL (movl_imm_xcc_xcc) FAST (movl_imm_xcc_xcc) }, + { TYPE (INSN_MOVGU_ICC_ICC), IDX (INSN_MOVGU_ICC_ICC), FULL (movgu_icc_icc) FAST (movgu_icc_icc) }, + { TYPE (INSN_MOVGU_IMM_ICC_ICC), IDX (INSN_MOVGU_IMM_ICC_ICC), FULL (movgu_imm_icc_icc) FAST (movgu_imm_icc_icc) }, + { TYPE (INSN_MOVGU_XCC_XCC), IDX (INSN_MOVGU_XCC_XCC), FULL (movgu_xcc_xcc) FAST (movgu_xcc_xcc) }, + { TYPE (INSN_MOVGU_IMM_XCC_XCC), IDX (INSN_MOVGU_IMM_XCC_XCC), FULL (movgu_imm_xcc_xcc) FAST (movgu_imm_xcc_xcc) }, + { TYPE (INSN_MOVLEU_ICC_ICC), IDX (INSN_MOVLEU_ICC_ICC), FULL (movleu_icc_icc) FAST (movleu_icc_icc) }, + { TYPE (INSN_MOVLEU_IMM_ICC_ICC), IDX (INSN_MOVLEU_IMM_ICC_ICC), FULL (movleu_imm_icc_icc) FAST (movleu_imm_icc_icc) }, + { TYPE (INSN_MOVLEU_XCC_XCC), IDX (INSN_MOVLEU_XCC_XCC), FULL (movleu_xcc_xcc) FAST (movleu_xcc_xcc) }, + { TYPE (INSN_MOVLEU_IMM_XCC_XCC), IDX (INSN_MOVLEU_IMM_XCC_XCC), FULL (movleu_imm_xcc_xcc) FAST (movleu_imm_xcc_xcc) }, + { TYPE (INSN_MOVCC_ICC_ICC), IDX (INSN_MOVCC_ICC_ICC), FULL (movcc_icc_icc) FAST (movcc_icc_icc) }, + { TYPE (INSN_MOVCC_IMM_ICC_ICC), IDX (INSN_MOVCC_IMM_ICC_ICC), FULL (movcc_imm_icc_icc) FAST (movcc_imm_icc_icc) }, + { TYPE (INSN_MOVCC_XCC_XCC), IDX (INSN_MOVCC_XCC_XCC), FULL (movcc_xcc_xcc) FAST (movcc_xcc_xcc) }, + { TYPE (INSN_MOVCC_IMM_XCC_XCC), IDX (INSN_MOVCC_IMM_XCC_XCC), FULL (movcc_imm_xcc_xcc) FAST (movcc_imm_xcc_xcc) }, + { TYPE (INSN_MOVCS_ICC_ICC), IDX (INSN_MOVCS_ICC_ICC), FULL (movcs_icc_icc) FAST (movcs_icc_icc) }, + { TYPE (INSN_MOVCS_IMM_ICC_ICC), IDX (INSN_MOVCS_IMM_ICC_ICC), FULL (movcs_imm_icc_icc) FAST (movcs_imm_icc_icc) }, + { TYPE (INSN_MOVCS_XCC_XCC), IDX (INSN_MOVCS_XCC_XCC), FULL (movcs_xcc_xcc) FAST (movcs_xcc_xcc) }, + { TYPE (INSN_MOVCS_IMM_XCC_XCC), IDX (INSN_MOVCS_IMM_XCC_XCC), FULL (movcs_imm_xcc_xcc) FAST (movcs_imm_xcc_xcc) }, + { TYPE (INSN_MOVPOS_ICC_ICC), IDX (INSN_MOVPOS_ICC_ICC), FULL (movpos_icc_icc) FAST (movpos_icc_icc) }, + { TYPE (INSN_MOVPOS_IMM_ICC_ICC), IDX (INSN_MOVPOS_IMM_ICC_ICC), FULL (movpos_imm_icc_icc) FAST (movpos_imm_icc_icc) }, + { TYPE (INSN_MOVPOS_XCC_XCC), IDX (INSN_MOVPOS_XCC_XCC), FULL (movpos_xcc_xcc) FAST (movpos_xcc_xcc) }, + { TYPE (INSN_MOVPOS_IMM_XCC_XCC), IDX (INSN_MOVPOS_IMM_XCC_XCC), FULL (movpos_imm_xcc_xcc) FAST (movpos_imm_xcc_xcc) }, + { TYPE (INSN_MOVNEG_ICC_ICC), IDX (INSN_MOVNEG_ICC_ICC), FULL (movneg_icc_icc) FAST (movneg_icc_icc) }, + { TYPE (INSN_MOVNEG_IMM_ICC_ICC), IDX (INSN_MOVNEG_IMM_ICC_ICC), FULL (movneg_imm_icc_icc) FAST (movneg_imm_icc_icc) }, + { TYPE (INSN_MOVNEG_XCC_XCC), IDX (INSN_MOVNEG_XCC_XCC), FULL (movneg_xcc_xcc) FAST (movneg_xcc_xcc) }, + { TYPE (INSN_MOVNEG_IMM_XCC_XCC), IDX (INSN_MOVNEG_IMM_XCC_XCC), FULL (movneg_imm_xcc_xcc) FAST (movneg_imm_xcc_xcc) }, + { TYPE (INSN_MOVVC_ICC_ICC), IDX (INSN_MOVVC_ICC_ICC), FULL (movvc_icc_icc) FAST (movvc_icc_icc) }, + { TYPE (INSN_MOVVC_IMM_ICC_ICC), IDX (INSN_MOVVC_IMM_ICC_ICC), FULL (movvc_imm_icc_icc) FAST (movvc_imm_icc_icc) }, + { TYPE (INSN_MOVVC_XCC_XCC), IDX (INSN_MOVVC_XCC_XCC), FULL (movvc_xcc_xcc) FAST (movvc_xcc_xcc) }, + { TYPE (INSN_MOVVC_IMM_XCC_XCC), IDX (INSN_MOVVC_IMM_XCC_XCC), FULL (movvc_imm_xcc_xcc) FAST (movvc_imm_xcc_xcc) }, + { TYPE (INSN_MOVVS_ICC_ICC), IDX (INSN_MOVVS_ICC_ICC), FULL (movvs_icc_icc) FAST (movvs_icc_icc) }, + { TYPE (INSN_MOVVS_IMM_ICC_ICC), IDX (INSN_MOVVS_IMM_ICC_ICC), FULL (movvs_imm_icc_icc) FAST (movvs_imm_icc_icc) }, + { TYPE (INSN_MOVVS_XCC_XCC), IDX (INSN_MOVVS_XCC_XCC), FULL (movvs_xcc_xcc) FAST (movvs_xcc_xcc) }, + { TYPE (INSN_MOVVS_IMM_XCC_XCC), IDX (INSN_MOVVS_IMM_XCC_XCC), FULL (movvs_imm_xcc_xcc) FAST (movvs_imm_xcc_xcc) }, + { TYPE (INSN_LDSB_REG_REG), IDX (INSN_LDSB_REG_REG), FULL (ldsb_reg_reg) FAST (ldsb_reg_reg) }, + { TYPE (INSN_LDSB_REG_IMM), IDX (INSN_LDSB_REG_IMM), FULL (ldsb_reg_imm) FAST (ldsb_reg_imm) }, + { TYPE (INSN_LDSB_REG_REG_ASI), IDX (INSN_LDSB_REG_REG_ASI), FULL (ldsb_reg_reg_asi) FAST (ldsb_reg_reg_asi) }, + { TYPE (INSN_LDUB_REG_REG), IDX (INSN_LDUB_REG_REG), FULL (ldub_reg_reg) FAST (ldub_reg_reg) }, + { TYPE (INSN_LDUB_REG_IMM), IDX (INSN_LDUB_REG_IMM), FULL (ldub_reg_imm) FAST (ldub_reg_imm) }, + { TYPE (INSN_LDUB_REG_REG_ASI), IDX (INSN_LDUB_REG_REG_ASI), FULL (ldub_reg_reg_asi) FAST (ldub_reg_reg_asi) }, + { TYPE (INSN_LDSH_REG_REG), IDX (INSN_LDSH_REG_REG), FULL (ldsh_reg_reg) FAST (ldsh_reg_reg) }, + { TYPE (INSN_LDSH_REG_IMM), IDX (INSN_LDSH_REG_IMM), FULL (ldsh_reg_imm) FAST (ldsh_reg_imm) }, + { TYPE (INSN_LDSH_REG_REG_ASI), IDX (INSN_LDSH_REG_REG_ASI), FULL (ldsh_reg_reg_asi) FAST (ldsh_reg_reg_asi) }, + { TYPE (INSN_LDUH_REG_REG), IDX (INSN_LDUH_REG_REG), FULL (lduh_reg_reg) FAST (lduh_reg_reg) }, + { TYPE (INSN_LDUH_REG_IMM), IDX (INSN_LDUH_REG_IMM), FULL (lduh_reg_imm) FAST (lduh_reg_imm) }, + { TYPE (INSN_LDUH_REG_REG_ASI), IDX (INSN_LDUH_REG_REG_ASI), FULL (lduh_reg_reg_asi) FAST (lduh_reg_reg_asi) }, + { TYPE (INSN_LDSW_REG_REG), IDX (INSN_LDSW_REG_REG), FULL (ldsw_reg_reg) FAST (ldsw_reg_reg) }, + { TYPE (INSN_LDSW_REG_IMM), IDX (INSN_LDSW_REG_IMM), FULL (ldsw_reg_imm) FAST (ldsw_reg_imm) }, + { TYPE (INSN_LDSW_REG_REG_ASI), IDX (INSN_LDSW_REG_REG_ASI), FULL (ldsw_reg_reg_asi) FAST (ldsw_reg_reg_asi) }, + { TYPE (INSN_LDUW_REG_REG), IDX (INSN_LDUW_REG_REG), FULL (lduw_reg_reg) FAST (lduw_reg_reg) }, + { TYPE (INSN_LDUW_REG_IMM), IDX (INSN_LDUW_REG_IMM), FULL (lduw_reg_imm) FAST (lduw_reg_imm) }, + { TYPE (INSN_LDUW_REG_REG_ASI), IDX (INSN_LDUW_REG_REG_ASI), FULL (lduw_reg_reg_asi) FAST (lduw_reg_reg_asi) }, + { TYPE (INSN_LDX_REG_REG), IDX (INSN_LDX_REG_REG), FULL (ldx_reg_reg) FAST (ldx_reg_reg) }, + { TYPE (INSN_LDX_REG_IMM), IDX (INSN_LDX_REG_IMM), FULL (ldx_reg_imm) FAST (ldx_reg_imm) }, + { TYPE (INSN_LDX_REG_REG_ASI), IDX (INSN_LDX_REG_REG_ASI), FULL (ldx_reg_reg_asi) FAST (ldx_reg_reg_asi) }, + { TYPE (INSN_LDD_REG_REG), IDX (INSN_LDD_REG_REG), FULL (ldd_reg_reg) FAST (ldd_reg_reg) }, + { TYPE (INSN_LDD_REG_IMM), IDX (INSN_LDD_REG_IMM), FULL (ldd_reg_imm) FAST (ldd_reg_imm) }, + { TYPE (INSN_LDD_REG_REG_ASI), IDX (INSN_LDD_REG_REG_ASI), FULL (ldd_reg_reg_asi) FAST (ldd_reg_reg_asi) }, + { TYPE (INSN_STB_REG_REG), IDX (INSN_STB_REG_REG), FULL (stb_reg_reg) FAST (stb_reg_reg) }, + { TYPE (INSN_STB_REG_IMM), IDX (INSN_STB_REG_IMM), FULL (stb_reg_imm) FAST (stb_reg_imm) }, + { TYPE (INSN_STB_REG_REG_ASI), IDX (INSN_STB_REG_REG_ASI), FULL (stb_reg_reg_asi) FAST (stb_reg_reg_asi) }, + { TYPE (INSN_STH_REG_REG), IDX (INSN_STH_REG_REG), FULL (sth_reg_reg) FAST (sth_reg_reg) }, + { TYPE (INSN_STH_REG_IMM), IDX (INSN_STH_REG_IMM), FULL (sth_reg_imm) FAST (sth_reg_imm) }, + { TYPE (INSN_STH_REG_REG_ASI), IDX (INSN_STH_REG_REG_ASI), FULL (sth_reg_reg_asi) FAST (sth_reg_reg_asi) }, + { TYPE (INSN_ST_REG_REG), IDX (INSN_ST_REG_REG), FULL (st_reg_reg) FAST (st_reg_reg) }, + { TYPE (INSN_ST_REG_IMM), IDX (INSN_ST_REG_IMM), FULL (st_reg_imm) FAST (st_reg_imm) }, + { TYPE (INSN_ST_REG_REG_ASI), IDX (INSN_ST_REG_REG_ASI), FULL (st_reg_reg_asi) FAST (st_reg_reg_asi) }, + { TYPE (INSN_STX_REG_REG), IDX (INSN_STX_REG_REG), FULL (stx_reg_reg) FAST (stx_reg_reg) }, + { TYPE (INSN_STX_REG_IMM), IDX (INSN_STX_REG_IMM), FULL (stx_reg_imm) FAST (stx_reg_imm) }, + { TYPE (INSN_STX_REG_REG_ASI), IDX (INSN_STX_REG_REG_ASI), FULL (stx_reg_reg_asi) FAST (stx_reg_reg_asi) }, + { TYPE (INSN_STD_REG_REG), IDX (INSN_STD_REG_REG), FULL (std_reg_reg) FAST (std_reg_reg) }, + { TYPE (INSN_STD_REG_IMM), IDX (INSN_STD_REG_IMM), FULL (std_reg_imm) FAST (std_reg_imm) }, + { TYPE (INSN_STD_REG_REG_ASI), IDX (INSN_STD_REG_REG_ASI), FULL (std_reg_reg_asi) FAST (std_reg_reg_asi) }, + { TYPE (INSN_FP_LD_REG_REG), IDX (INSN_FP_LD_REG_REG), FULL (fp_ld_reg_reg) FAST (fp_ld_reg_reg) }, + { TYPE (INSN_FP_LD_REG_IMM), IDX (INSN_FP_LD_REG_IMM), FULL (fp_ld_reg_imm) FAST (fp_ld_reg_imm) }, + { TYPE (INSN_FP_LD_REG_REG_ASI), IDX (INSN_FP_LD_REG_REG_ASI), FULL (fp_ld_reg_reg_asi) FAST (fp_ld_reg_reg_asi) }, + { TYPE (INSN_SETHI), IDX (INSN_SETHI), FULL (sethi) FAST (sethi) }, + { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) }, + { TYPE (INSN_ADD_IMM), IDX (INSN_ADD_IMM), FULL (add_imm) FAST (add_imm) }, + { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) }, + { TYPE (INSN_SUB_IMM), IDX (INSN_SUB_IMM), FULL (sub_imm) FAST (sub_imm) }, + { TYPE (INSN_ADDCC), IDX (INSN_ADDCC), FULL (addcc) FAST (addcc) }, + { TYPE (INSN_ADDCC_IMM), IDX (INSN_ADDCC_IMM), FULL (addcc_imm) FAST (addcc_imm) }, + { TYPE (INSN_SUBCC), IDX (INSN_SUBCC), FULL (subcc) FAST (subcc) }, + { TYPE (INSN_SUBCC_IMM), IDX (INSN_SUBCC_IMM), FULL (subcc_imm) FAST (subcc_imm) }, + { TYPE (INSN_ADDC), IDX (INSN_ADDC), FULL (addc) FAST (addc) }, + { TYPE (INSN_ADDC_IMM), IDX (INSN_ADDC_IMM), FULL (addc_imm) FAST (addc_imm) }, + { TYPE (INSN_SUBC), IDX (INSN_SUBC), FULL (subc) FAST (subc) }, + { TYPE (INSN_SUBC_IMM), IDX (INSN_SUBC_IMM), FULL (subc_imm) FAST (subc_imm) }, + { TYPE (INSN_ADDCCC), IDX (INSN_ADDCCC), FULL (addccc) FAST (addccc) }, + { TYPE (INSN_ADDCCC_IMM), IDX (INSN_ADDCCC_IMM), FULL (addccc_imm) FAST (addccc_imm) }, + { TYPE (INSN_SUBCCC), IDX (INSN_SUBCCC), FULL (subccc) FAST (subccc) }, + { TYPE (INSN_SUBCCC_IMM), IDX (INSN_SUBCCC_IMM), FULL (subccc_imm) FAST (subccc_imm) }, + { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) }, + { TYPE (INSN_AND_IMM), IDX (INSN_AND_IMM), FULL (and_imm) FAST (and_imm) }, + { TYPE (INSN_ANDCC), IDX (INSN_ANDCC), FULL (andcc) FAST (andcc) }, + { TYPE (INSN_ANDCC_IMM), IDX (INSN_ANDCC_IMM), FULL (andcc_imm) FAST (andcc_imm) }, + { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) }, + { TYPE (INSN_OR_IMM), IDX (INSN_OR_IMM), FULL (or_imm) FAST (or_imm) }, + { TYPE (INSN_ORCC), IDX (INSN_ORCC), FULL (orcc) FAST (orcc) }, + { TYPE (INSN_ORCC_IMM), IDX (INSN_ORCC_IMM), FULL (orcc_imm) FAST (orcc_imm) }, + { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) }, + { TYPE (INSN_XOR_IMM), IDX (INSN_XOR_IMM), FULL (xor_imm) FAST (xor_imm) }, + { TYPE (INSN_XORCC), IDX (INSN_XORCC), FULL (xorcc) FAST (xorcc) }, + { TYPE (INSN_XORCC_IMM), IDX (INSN_XORCC_IMM), FULL (xorcc_imm) FAST (xorcc_imm) }, + { TYPE (INSN_ANDN), IDX (INSN_ANDN), FULL (andn) FAST (andn) }, + { TYPE (INSN_ANDN_IMM), IDX (INSN_ANDN_IMM), FULL (andn_imm) FAST (andn_imm) }, + { TYPE (INSN_ANDNCC), IDX (INSN_ANDNCC), FULL (andncc) FAST (andncc) }, + { TYPE (INSN_ANDNCC_IMM), IDX (INSN_ANDNCC_IMM), FULL (andncc_imm) FAST (andncc_imm) }, + { TYPE (INSN_ORN), IDX (INSN_ORN), FULL (orn) FAST (orn) }, + { TYPE (INSN_ORN_IMM), IDX (INSN_ORN_IMM), FULL (orn_imm) FAST (orn_imm) }, + { TYPE (INSN_ORNCC), IDX (INSN_ORNCC), FULL (orncc) FAST (orncc) }, + { TYPE (INSN_ORNCC_IMM), IDX (INSN_ORNCC_IMM), FULL (orncc_imm) FAST (orncc_imm) }, + { TYPE (INSN_XNOR), IDX (INSN_XNOR), FULL (xnor) FAST (xnor) }, + { TYPE (INSN_XNOR_IMM), IDX (INSN_XNOR_IMM), FULL (xnor_imm) FAST (xnor_imm) }, + { TYPE (INSN_XNORCC), IDX (INSN_XNORCC), FULL (xnorcc) FAST (xnorcc) }, + { TYPE (INSN_XNORCC_IMM), IDX (INSN_XNORCC_IMM), FULL (xnorcc_imm) FAST (xnorcc_imm) }, + { TYPE (INSN_SLL), IDX (INSN_SLL), FULL (sll) FAST (sll) }, + { TYPE (INSN_SLL_IMM), IDX (INSN_SLL_IMM), FULL (sll_imm) FAST (sll_imm) }, + { TYPE (INSN_SRL), IDX (INSN_SRL), FULL (srl) FAST (srl) }, + { TYPE (INSN_SRL_IMM), IDX (INSN_SRL_IMM), FULL (srl_imm) FAST (srl_imm) }, + { TYPE (INSN_SRA), IDX (INSN_SRA), FULL (sra) FAST (sra) }, + { TYPE (INSN_SRA_IMM), IDX (INSN_SRA_IMM), FULL (sra_imm) FAST (sra_imm) }, + { TYPE (INSN_SMUL), IDX (INSN_SMUL), FULL (smul) FAST (smul) }, + { TYPE (INSN_SMUL_IMM), IDX (INSN_SMUL_IMM), FULL (smul_imm) FAST (smul_imm) }, + { TYPE (INSN_SMUL_CC), IDX (INSN_SMUL_CC), FULL (smul_cc) FAST (smul_cc) }, + { TYPE (INSN_SMUL_CC_IMM), IDX (INSN_SMUL_CC_IMM), FULL (smul_cc_imm) FAST (smul_cc_imm) }, + { TYPE (INSN_UMUL), IDX (INSN_UMUL), FULL (umul) FAST (umul) }, + { TYPE (INSN_UMUL_IMM), IDX (INSN_UMUL_IMM), FULL (umul_imm) FAST (umul_imm) }, + { TYPE (INSN_UMUL_CC), IDX (INSN_UMUL_CC), FULL (umul_cc) FAST (umul_cc) }, + { TYPE (INSN_UMUL_CC_IMM), IDX (INSN_UMUL_CC_IMM), FULL (umul_cc_imm) FAST (umul_cc_imm) }, + { TYPE (INSN_MULSCC), IDX (INSN_MULSCC), FULL (mulscc) FAST (mulscc) }, + { TYPE (INSN_SAVE), IDX (INSN_SAVE), FULL (save) FAST (save) }, + { TYPE (INSN_SAVE_IMM), IDX (INSN_SAVE_IMM), FULL (save_imm) FAST (save_imm) }, + { TYPE (INSN_RESTORE), IDX (INSN_RESTORE), FULL (restore) FAST (restore) }, + { TYPE (INSN_RESTORE_IMM), IDX (INSN_RESTORE_IMM), FULL (restore_imm) FAST (restore_imm) }, + { TYPE (INSN_RETT), IDX (INSN_RETT), FULL (rett) FAST (rett) }, + { TYPE (INSN_RETT_IMM), IDX (INSN_RETT_IMM), FULL (rett_imm) FAST (rett_imm) }, + { TYPE (INSN_UNIMP), IDX (INSN_UNIMP), FULL (unimp) FAST (unimp) }, + { TYPE (INSN_CALL), IDX (INSN_CALL), FULL (call) FAST (call) }, + { TYPE (INSN_JMPL), IDX (INSN_JMPL), FULL (jmpl) FAST (jmpl) }, + { TYPE (INSN_JMPL_IMM), IDX (INSN_JMPL_IMM), FULL (jmpl_imm) FAST (jmpl_imm) }, + { TYPE (INSN_BA), IDX (INSN_BA), FULL (ba) FAST (ba) }, + { TYPE (INSN_TA), IDX (INSN_TA), FULL (ta) FAST (ta) }, + { TYPE (INSN_TA_IMM), IDX (INSN_TA_IMM), FULL (ta_imm) FAST (ta_imm) }, + { TYPE (INSN_BN), IDX (INSN_BN), FULL (bn) FAST (bn) }, + { TYPE (INSN_TN), IDX (INSN_TN), FULL (tn) FAST (tn) }, + { TYPE (INSN_TN_IMM), IDX (INSN_TN_IMM), FULL (tn_imm) FAST (tn_imm) }, + { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) }, + { TYPE (INSN_TNE), IDX (INSN_TNE), FULL (tne) FAST (tne) }, + { TYPE (INSN_TNE_IMM), IDX (INSN_TNE_IMM), FULL (tne_imm) FAST (tne_imm) }, + { TYPE (INSN_BE), IDX (INSN_BE), FULL (be) FAST (be) }, + { TYPE (INSN_TE), IDX (INSN_TE), FULL (te) FAST (te) }, + { TYPE (INSN_TE_IMM), IDX (INSN_TE_IMM), FULL (te_imm) FAST (te_imm) }, + { TYPE (INSN_BG), IDX (INSN_BG), FULL (bg) FAST (bg) }, + { TYPE (INSN_TG), IDX (INSN_TG), FULL (tg) FAST (tg) }, + { TYPE (INSN_TG_IMM), IDX (INSN_TG_IMM), FULL (tg_imm) FAST (tg_imm) }, + { TYPE (INSN_BLE), IDX (INSN_BLE), FULL (ble) FAST (ble) }, + { TYPE (INSN_TLE), IDX (INSN_TLE), FULL (tle) FAST (tle) }, + { TYPE (INSN_TLE_IMM), IDX (INSN_TLE_IMM), FULL (tle_imm) FAST (tle_imm) }, + { TYPE (INSN_BGE), IDX (INSN_BGE), FULL (bge) FAST (bge) }, + { TYPE (INSN_TGE), IDX (INSN_TGE), FULL (tge) FAST (tge) }, + { TYPE (INSN_TGE_IMM), IDX (INSN_TGE_IMM), FULL (tge_imm) FAST (tge_imm) }, + { TYPE (INSN_BL), IDX (INSN_BL), FULL (bl) FAST (bl) }, + { TYPE (INSN_TL), IDX (INSN_TL), FULL (tl) FAST (tl) }, + { TYPE (INSN_TL_IMM), IDX (INSN_TL_IMM), FULL (tl_imm) FAST (tl_imm) }, + { TYPE (INSN_BGU), IDX (INSN_BGU), FULL (bgu) FAST (bgu) }, + { TYPE (INSN_TGU), IDX (INSN_TGU), FULL (tgu) FAST (tgu) }, + { TYPE (INSN_TGU_IMM), IDX (INSN_TGU_IMM), FULL (tgu_imm) FAST (tgu_imm) }, + { TYPE (INSN_BLEU), IDX (INSN_BLEU), FULL (bleu) FAST (bleu) }, + { TYPE (INSN_TLEU), IDX (INSN_TLEU), FULL (tleu) FAST (tleu) }, + { TYPE (INSN_TLEU_IMM), IDX (INSN_TLEU_IMM), FULL (tleu_imm) FAST (tleu_imm) }, + { TYPE (INSN_BCC), IDX (INSN_BCC), FULL (bcc) FAST (bcc) }, + { TYPE (INSN_TCC), IDX (INSN_TCC), FULL (tcc) FAST (tcc) }, + { TYPE (INSN_TCC_IMM), IDX (INSN_TCC_IMM), FULL (tcc_imm) FAST (tcc_imm) }, + { TYPE (INSN_BCS), IDX (INSN_BCS), FULL (bcs) FAST (bcs) }, + { TYPE (INSN_TCS), IDX (INSN_TCS), FULL (tcs) FAST (tcs) }, + { TYPE (INSN_TCS_IMM), IDX (INSN_TCS_IMM), FULL (tcs_imm) FAST (tcs_imm) }, + { TYPE (INSN_BPOS), IDX (INSN_BPOS), FULL (bpos) FAST (bpos) }, + { TYPE (INSN_TPOS), IDX (INSN_TPOS), FULL (tpos) FAST (tpos) }, + { TYPE (INSN_TPOS_IMM), IDX (INSN_TPOS_IMM), FULL (tpos_imm) FAST (tpos_imm) }, + { TYPE (INSN_BNEG), IDX (INSN_BNEG), FULL (bneg) FAST (bneg) }, + { TYPE (INSN_TNEG), IDX (INSN_TNEG), FULL (tneg) FAST (tneg) }, + { TYPE (INSN_TNEG_IMM), IDX (INSN_TNEG_IMM), FULL (tneg_imm) FAST (tneg_imm) }, + { TYPE (INSN_BVC), IDX (INSN_BVC), FULL (bvc) FAST (bvc) }, + { TYPE (INSN_TVC), IDX (INSN_TVC), FULL (tvc) FAST (tvc) }, + { TYPE (INSN_TVC_IMM), IDX (INSN_TVC_IMM), FULL (tvc_imm) FAST (tvc_imm) }, + { TYPE (INSN_BVS), IDX (INSN_BVS), FULL (bvs) FAST (bvs) }, + { TYPE (INSN_TVS), IDX (INSN_TVS), FULL (tvs) FAST (tvs) }, + { TYPE (INSN_TVS_IMM), IDX (INSN_TVS_IMM), FULL (tvs_imm) FAST (tvs_imm) }, + { TYPE (INSN_LDSTUB_REG_REG), IDX (INSN_LDSTUB_REG_REG), FULL (ldstub_reg_reg) FAST (ldstub_reg_reg) }, + { TYPE (INSN_LDSTUB_REG_IMM), IDX (INSN_LDSTUB_REG_IMM), FULL (ldstub_reg_imm) FAST (ldstub_reg_imm) }, + { TYPE (INSN_LDSTUB_REG_REG_ASI), IDX (INSN_LDSTUB_REG_REG_ASI), FULL (ldstub_reg_reg_asi) FAST (ldstub_reg_reg_asi) }, + { TYPE (INSN_SWAP_REG_REG), IDX (INSN_SWAP_REG_REG), FULL (swap_reg_reg) FAST (swap_reg_reg) }, + { TYPE (INSN_SWAP_REG_IMM), IDX (INSN_SWAP_REG_IMM), FULL (swap_reg_imm) FAST (swap_reg_imm) }, + { TYPE (INSN_SWAP_REG_REG_ASI), IDX (INSN_SWAP_REG_REG_ASI), FULL (swap_reg_reg_asi) FAST (swap_reg_reg_asi) }, +}; + +static const struct insn_sem sparc64_insn_sem_invalid = +{ + VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) +}; + +#undef IDX +#undef TYPE + +/* Initialize an IDESC from the compile-time computable parts. */ + +static INLINE void +init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) +{ + const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; + + id->num = t->index; + if ((int) t->type <= 0) + id->idata = & cgen_virtual_insn_table[- (int) t->type]; + else + id->idata = & insn_table[t->type]; + id->attrs = CGEN_INSN_ATTRS (id->idata); + /* Oh my god, a magic number. */ + id->length = CGEN_INSN_BITSIZE (id->idata) / 8; +#if ! WITH_SEM_SWITCH_FULL + id->sem_full = t->sem_full; +#endif +#if WITH_FAST && ! WITH_SEM_SWITCH_FAST + id->sem_fast = t->sem_fast; +#endif +#if WITH_PROFILE_MODEL_P + id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; + { + SIM_DESC sd = CPU_STATE (cpu); + SIM_ASSERT (t->index == id->timing->num); + } +#endif +} + +/* Initialize the instruction descriptor table. */ + +void +sparc64_init_idesc_table (SIM_CPU *cpu) +{ + IDESC *id,*tabend; + const struct insn_sem *t,*tend; + int tabsize = SPARC64_INSN_MAX; + IDESC *table = sparc64_insn_data; + + memset (table, 0, tabsize * sizeof (IDESC)); + + /* First set all entries to the `invalid insn'. */ + t = & sparc64_insn_sem_invalid; + for (id = table, tabend = table + tabsize; id < tabend; ++id) + init_idesc (cpu, id, t); + + /* Now fill in the values for the chosen cpu. */ + for (t = sparc64_insn_sem, tend = t + sizeof (sparc64_insn_sem) / sizeof (*t); + t != tend; ++t) + { + init_idesc (cpu, & table[t->index], t); + } + + /* Link the IDESC table into the cpu. */ + CPU_IDESC (cpu) = table; +} + +#define GOTO_EXTRACT(id) goto extract + +/* The decoder needs a slightly different computed goto switch control. */ +#ifdef __GNUC__ +#define DECODE_SWITCH(N, X) goto *labels_##N[X]; +#else +#define DECODE_SWITCH(N, X) switch (X) +#endif + +/* Given an instruction, return a pointer to its IDESC entry. */ + +const IDESC * +sparc64_decode (SIM_CPU *current_cpu, IADDR pc, + CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + ARGBUF *abuf) +{ + /* Result. */ + const IDESC *idecode; + + { +#define I(insn) & sparc64_insn_data[CONCAT2 (SPARC64_,insn)] + CGEN_INSN_INT insn = base_insn; + static const IDESC *idecode_invalid = I (INSN_X_INVALID); + + { +#ifdef __GNUC__ + static const void *labels_0[256] = { + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && case_0_12, && case_0_13, && default_0, && default_0, + && case_0_16, && case_0_17, && case_0_18, && case_0_19, + && case_0_20, && case_0_21, && case_0_22, && case_0_23, + && case_0_24, && case_0_25, && case_0_26, && case_0_27, + && case_0_28, && case_0_29, && case_0_30, && case_0_31, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && case_0_128, && case_0_129, && case_0_130, && case_0_131, + && case_0_132, && case_0_133, && case_0_134, && case_0_135, + && case_0_136, && default_0, && case_0_138, && case_0_139, + && case_0_140, && default_0, && default_0, && default_0, + && case_0_144, && case_0_145, && case_0_146, && case_0_147, + && case_0_148, && case_0_149, && case_0_150, && case_0_151, + && case_0_152, && default_0, && case_0_154, && case_0_155, + && case_0_156, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && case_0_165, && case_0_166, && case_0_167, + && default_0, && default_0, && default_0, && default_0, + && case_0_172, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && case_0_184, && case_0_185, && case_0_186, && case_0_187, + && case_0_188, && case_0_189, && case_0_190, && default_0, + && case_0_192, && case_0_193, && case_0_194, && case_0_195, + && case_0_196, && case_0_197, && case_0_198, && case_0_199, + && case_0_200, && case_0_201, && case_0_202, && case_0_203, + && default_0, && case_0_205, && case_0_206, && case_0_207, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && case_0_224, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + }; +#endif + static const IDESC * insns[256] = { + I (INSN_UNIMP), I (INSN_UNIMP), + I (INSN_UNIMP), I (INSN_UNIMP), + I (INSN_UNIMP), I (INSN_UNIMP), + I (INSN_UNIMP), I (INSN_UNIMP), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + 0, 0, + I (INSN_X_INVALID), I (INSN_X_INVALID), + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + I (INSN_SETHI), I (INSN_SETHI), + I (INSN_SETHI), I (INSN_SETHI), + I (INSN_SETHI), I (INSN_SETHI), + I (INSN_SETHI), I (INSN_SETHI), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, I (INSN_X_INVALID), + 0, 0, + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, I (INSN_X_INVALID), + 0, 0, + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MULSCC), 0, + 0, 0, + I (INSN_MEMBAR), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_FLUSHW), + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_IMPDEP1), I (INSN_IMPDEP2), + 0, 0, + 0, 0, + 0, 0, + 0, I (INSN_X_INVALID), + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + I (INSN_X_INVALID), 0, + 0, 0, + I (INSN_LDUW_REG_REG_ASI), I (INSN_LDUB_REG_REG_ASI), + I (INSN_LDUH_REG_REG_ASI), I (INSN_LDD_REG_REG_ASI), + I (INSN_ST_REG_REG_ASI), I (INSN_STB_REG_REG_ASI), + I (INSN_STH_REG_REG_ASI), I (INSN_STD_REG_REG_ASI), + I (INSN_LDSW_REG_REG_ASI), I (INSN_LDSB_REG_REG_ASI), + I (INSN_LDSH_REG_REG_ASI), I (INSN_LDX_REG_REG_ASI), + I (INSN_X_INVALID), I (INSN_LDSTUB_REG_REG_ASI), + I (INSN_STX_REG_REG_ASI), I (INSN_SWAP_REG_REG_ASI), + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_FP_LD_REG_REG_ASI), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val; + val = (((insn >> 24) & (3 << 6)) | ((insn >> 19) & (63 << 0))); + DECODE_SWITCH (0, val) + { + CASE (0, 12) : /* fall through */ + CASE (0, 13) : + { + static const IDESC * insns[16] = { + I (INSN_BPCC_BN), I (INSN_BPCC_BE), + I (INSN_BPCC_BLE), I (INSN_BPCC_BL), + I (INSN_BPCC_BLEU), I (INSN_BPCC_BCS), + I (INSN_BPCC_BNEG), I (INSN_BPCC_BVS), + I (INSN_BPCC_BA), I (INSN_BPCC_BNE), + I (INSN_BPCC_BG), I (INSN_BPCC_BGE), + I (INSN_BPCC_BGU), I (INSN_BPCC_BCC), + I (INSN_BPCC_BPOS), I (INSN_BPCC_BVC), + }; + unsigned int val = (((insn >> 25) & (15 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 16) : /* fall through */ + CASE (0, 17) : /* fall through */ + CASE (0, 18) : /* fall through */ + CASE (0, 19) : /* fall through */ + CASE (0, 20) : /* fall through */ + CASE (0, 21) : /* fall through */ + CASE (0, 22) : /* fall through */ + CASE (0, 23) : + { + static const IDESC * insns[16] = { + I (INSN_BN), I (INSN_BE), + I (INSN_BLE), I (INSN_BL), + I (INSN_BLEU), I (INSN_BCS), + I (INSN_BNEG), I (INSN_BVS), + I (INSN_BA), I (INSN_BNE), + I (INSN_BG), I (INSN_BGE), + I (INSN_BGU), I (INSN_BCC), + I (INSN_BPOS), I (INSN_BVC), + }; + unsigned int val = (((insn >> 25) & (15 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 24) : /* fall through */ + CASE (0, 25) : /* fall through */ + CASE (0, 26) : /* fall through */ + CASE (0, 27) : /* fall through */ + CASE (0, 28) : /* fall through */ + CASE (0, 29) : /* fall through */ + CASE (0, 30) : /* fall through */ + CASE (0, 31) : + { + static const IDESC * insns[8] = { + I (INSN_X_INVALID), I (INSN_BEQZ), + I (INSN_BLEZ), I (INSN_BLTZ), + I (INSN_X_INVALID), I (INSN_BNEZ), + I (INSN_BGTZ), I (INSN_BGEZ), + }; + unsigned int val = (((insn >> 25) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 128) : + { + static const IDESC * insns[2] = { + I (INSN_ADD), I (INSN_ADD_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 129) : + { + static const IDESC * insns[2] = { + I (INSN_AND), I (INSN_AND_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 130) : + { + static const IDESC * insns[2] = { + I (INSN_OR), I (INSN_OR_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 131) : + { + static const IDESC * insns[2] = { + I (INSN_XOR), I (INSN_XOR_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 132) : + { + static const IDESC * insns[2] = { + I (INSN_SUB), I (INSN_SUB_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 133) : + { + static const IDESC * insns[2] = { + I (INSN_ANDN), I (INSN_ANDN_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 134) : + { + static const IDESC * insns[2] = { + I (INSN_ORN), I (INSN_ORN_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 135) : + { + static const IDESC * insns[2] = { + I (INSN_XNOR), I (INSN_XNOR_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 136) : + { + static const IDESC * insns[2] = { + I (INSN_ADDC), I (INSN_ADDC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 138) : + { + static const IDESC * insns[2] = { + I (INSN_UMUL), I (INSN_UMUL_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 139) : + { + static const IDESC * insns[2] = { + I (INSN_SMUL), I (INSN_SMUL_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 140) : + { + static const IDESC * insns[2] = { + I (INSN_SUBC), I (INSN_SUBC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 144) : + { + static const IDESC * insns[2] = { + I (INSN_ADDCC), I (INSN_ADDCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 145) : + { + static const IDESC * insns[2] = { + I (INSN_ANDCC), I (INSN_ANDCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 146) : + { + static const IDESC * insns[2] = { + I (INSN_ORCC), I (INSN_ORCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 147) : + { + static const IDESC * insns[2] = { + I (INSN_XORCC), I (INSN_XORCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 148) : + { + static const IDESC * insns[2] = { + I (INSN_SUBCC), I (INSN_SUBCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 149) : + { + static const IDESC * insns[2] = { + I (INSN_ANDNCC), I (INSN_ANDNCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 150) : + { + static const IDESC * insns[2] = { + I (INSN_ORNCC), I (INSN_ORNCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 151) : + { + static const IDESC * insns[2] = { + I (INSN_XNORCC), I (INSN_XNORCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 152) : + { + static const IDESC * insns[2] = { + I (INSN_ADDCCC), I (INSN_ADDCCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 154) : + { + static const IDESC * insns[2] = { + I (INSN_UMUL_CC), I (INSN_UMUL_CC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 155) : + { + static const IDESC * insns[2] = { + I (INSN_SMUL_CC), I (INSN_SMUL_CC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 156) : + { + static const IDESC * insns[2] = { + I (INSN_SUBCCC), I (INSN_SUBCCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 165) : + { + static const IDESC * insns[2] = { + I (INSN_SLL), I (INSN_SLL_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 166) : + { + static const IDESC * insns[2] = { + I (INSN_SRL), I (INSN_SRL_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 167) : + { + static const IDESC * insns[2] = { + I (INSN_SRA), I (INSN_SRA_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 172) : + { +#ifdef __GNUC__ + static const void *labels_0_172[16] = { + && case_0_172_0, && case_0_172_1, && case_0_172_2, && case_0_172_3, + && case_0_172_4, && case_0_172_5, && case_0_172_6, && case_0_172_7, + && case_0_172_8, && case_0_172_9, && case_0_172_10, && case_0_172_11, + && case_0_172_12, && case_0_172_13, && case_0_172_14, && case_0_172_15, + }; +#endif + unsigned int val; + val = (((insn >> 25) & (15 << 0))); + DECODE_SWITCH (0_172, val) + { + CASE (0_172, 0) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVN_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVN_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVN_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVN_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 1) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVE_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVE_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVE_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVE_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 2) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVLE_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVLE_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVLE_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVLE_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 3) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVL_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVL_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVL_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVL_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 4) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVLEU_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVLEU_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVLEU_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVLEU_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 5) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVCS_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVCS_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVCS_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVCS_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 6) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVNEG_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVNEG_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVNEG_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVNEG_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 7) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVVS_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVVS_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVVS_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVVS_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 8) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVA_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVA_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVA_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVA_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 9) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVNE_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVNE_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVNE_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVNE_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 10) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVG_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVG_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVG_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVG_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 11) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVGE_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVGE_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVGE_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVGE_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 12) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVGU_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVGU_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVGU_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVGU_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 13) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVCC_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVCC_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVCC_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVCC_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 14) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVPOS_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVPOS_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVPOS_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVPOS_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_172, 15) : + { + static const IDESC * insns[16] = { + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MOVVC_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVVC_XCC_XCC), I (INSN_X_INVALID), + I (INSN_MOVVC_IMM_ICC_ICC), I (INSN_X_INVALID), + I (INSN_MOVVC_IMM_XCC_XCC), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0_172) : + idecode = idecode_invalid; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0_172) + } + CASE (0, 184) : + { + static const IDESC * insns[2] = { + I (INSN_JMPL), I (INSN_JMPL_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 185) : + { +#ifdef __GNUC__ + static const void *labels_0_185[16] = { + && case_0_185_0, && default_0_185, && default_0_185, && default_0_185, + && default_0_185, && default_0_185, && default_0_185, && default_0_185, + && default_0_185, && default_0_185, && default_0_185, && default_0_185, + && default_0_185, && default_0_185, && default_0_185, && default_0_185, + }; +#endif + static const IDESC * insns[16] = { + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val; + val = (((insn >> 26) & (15 << 0))); + DECODE_SWITCH (0_185, val) + { + CASE (0_185, 0) : + { + static const IDESC * insns[4] = { + I (INSN_RETT), I (INSN_RETT_IMM), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0_185) : + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0_185) + } + CASE (0, 186) : + { +#ifdef __GNUC__ + static const void *labels_0_186[16] = { + && case_0_186_0, && case_0_186_1, && case_0_186_2, && case_0_186_3, + && case_0_186_4, && case_0_186_5, && case_0_186_6, && case_0_186_7, + && default_0_186, && default_0_186, && default_0_186, && default_0_186, + && default_0_186, && default_0_186, && default_0_186, && default_0_186, + }; +#endif + static const IDESC * insns[16] = { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val; + val = (((insn >> 26) & (15 << 0))); + DECODE_SWITCH (0_186, val) + { + CASE (0_186, 0) : + { + static const IDESC * insns[4] = { + I (INSN_TN), I (INSN_TN_IMM), + I (INSN_TE), I (INSN_TE_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 1) : + { + static const IDESC * insns[4] = { + I (INSN_TLE), I (INSN_TLE_IMM), + I (INSN_TL), I (INSN_TL_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 2) : + { + static const IDESC * insns[4] = { + I (INSN_TLEU), I (INSN_TLEU_IMM), + I (INSN_TCS), I (INSN_TCS_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 3) : + { + static const IDESC * insns[4] = { + I (INSN_TNEG), I (INSN_TNEG_IMM), + I (INSN_TVS), I (INSN_TVS_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 4) : + { + static const IDESC * insns[4] = { + I (INSN_TA), I (INSN_TA_IMM), + I (INSN_TNE), I (INSN_TNE_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 5) : + { + static const IDESC * insns[4] = { + I (INSN_TG), I (INSN_TG_IMM), + I (INSN_TGE), I (INSN_TGE_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 6) : + { + static const IDESC * insns[4] = { + I (INSN_TGU), I (INSN_TGU_IMM), + I (INSN_TCC), I (INSN_TCC_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 7) : + { + static const IDESC * insns[4] = { + I (INSN_TPOS), I (INSN_TPOS_IMM), + I (INSN_TVC), I (INSN_TVC_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0_186) : + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0_186) + } + CASE (0, 187) : + { +#ifdef __GNUC__ + static const void *labels_0_187[16] = { + && case_0_187_0, && default_0_187, && default_0_187, && default_0_187, + && default_0_187, && default_0_187, && default_0_187, && default_0_187, + && default_0_187, && default_0_187, && default_0_187, && default_0_187, + && default_0_187, && default_0_187, && default_0_187, && default_0_187, + }; +#endif + static const IDESC * insns[16] = { + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val; + val = (((insn >> 26) & (15 << 0))); + DECODE_SWITCH (0_187, val) + { + CASE (0_187, 0) : + { + static const IDESC * insns[4] = { + I (INSN_FLUSH), I (INSN_FLUSH_IMM), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0_187) : + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0_187) + } + CASE (0, 188) : + { + static const IDESC * insns[2] = { + I (INSN_SAVE), I (INSN_SAVE_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 189) : + { + static const IDESC * insns[2] = { + I (INSN_RESTORE), I (INSN_RESTORE_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 190) : + { +#ifdef __GNUC__ + static const void *labels_0_190[16] = { + && case_0_190_0, && default_0_190, && default_0_190, && default_0_190, + && default_0_190, && default_0_190, && default_0_190, && default_0_190, + && default_0_190, && default_0_190, && default_0_190, && default_0_190, + && default_0_190, && default_0_190, && default_0_190, && default_0_190, + }; +#endif + static const IDESC * insns[16] = { + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val; + val = (((insn >> 26) & (15 << 0))); + DECODE_SWITCH (0_190, val) + { + CASE (0_190, 0) : + { + static const IDESC * insns[2] = { + I (INSN_DONE), I (INSN_RETRY), + }; + unsigned int val = (((insn >> 25) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0_190) : + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0_190) + } + CASE (0, 192) : + { + static const IDESC * insns[2] = { + I (INSN_LDUW_REG_REG), I (INSN_LDUW_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 193) : + { + static const IDESC * insns[2] = { + I (INSN_LDUB_REG_REG), I (INSN_LDUB_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 194) : + { + static const IDESC * insns[2] = { + I (INSN_LDUH_REG_REG), I (INSN_LDUH_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 195) : + { + static const IDESC * insns[2] = { + I (INSN_LDD_REG_REG), I (INSN_LDD_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 196) : + { + static const IDESC * insns[2] = { + I (INSN_ST_REG_REG), I (INSN_ST_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 197) : + { + static const IDESC * insns[2] = { + I (INSN_STB_REG_REG), I (INSN_STB_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 198) : + { + static const IDESC * insns[2] = { + I (INSN_STH_REG_REG), I (INSN_STH_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 199) : + { + static const IDESC * insns[2] = { + I (INSN_STD_REG_REG), I (INSN_STD_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 200) : + { + static const IDESC * insns[2] = { + I (INSN_LDSW_REG_REG), I (INSN_LDSW_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 201) : + { + static const IDESC * insns[2] = { + I (INSN_LDSB_REG_REG), I (INSN_LDSB_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 202) : + { + static const IDESC * insns[2] = { + I (INSN_LDSH_REG_REG), I (INSN_LDSH_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 203) : + { + static const IDESC * insns[2] = { + I (INSN_LDX_REG_REG), I (INSN_LDX_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 205) : + { + static const IDESC * insns[2] = { + I (INSN_LDSTUB_REG_REG), I (INSN_LDSTUB_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 206) : + { + static const IDESC * insns[2] = { + I (INSN_STX_REG_REG), I (INSN_STX_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 207) : + { + static const IDESC * insns[2] = { + I (INSN_SWAP_REG_REG), I (INSN_SWAP_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 224) : + { + static const IDESC * insns[2] = { + I (INSN_FP_LD_REG_REG), I (INSN_FP_LD_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0) : + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0) + } +#undef I +#undef E + } + + /* Extraction is defered until the semantic code. */ + + extract: + return idecode; +} diff --git a/sim/sparc/decode64.h b/sim/sparc/decode64.h new file mode 100644 index 0000000000..373d5e3bcc --- /dev/null +++ b/sim/sparc/decode64.h @@ -0,0 +1,385 @@ +/* Decode header for sparc64. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#ifndef SPARC64_DECODE_H +#define SPARC64_DECODE_H + +extern const IDESC *sparc64_decode (SIM_CPU *, IADDR, + CGEN_INSN_INT, CGEN_INSN_INT, + ARGBUF *); +extern void sparc64_init_idesc_table (SIM_CPU *); + +/* Enum declaration for instructions in cpu family sparc64. */ +typedef enum sparc64_insn_type { + SPARC64_INSN_X_INVALID, SPARC64_INSN_X_AFTER, SPARC64_INSN_X_BEFORE, SPARC64_INSN_X_CTI_CHAIN + , SPARC64_INSN_X_CHAIN, SPARC64_INSN_X_BEGIN, SPARC64_INSN_BEQZ, SPARC64_INSN_BGEZ + , SPARC64_INSN_BGTZ, SPARC64_INSN_BLEZ, SPARC64_INSN_BLTZ, SPARC64_INSN_BNEZ + , SPARC64_INSN_BPCC_BA, SPARC64_INSN_BPCC_BN, SPARC64_INSN_BPCC_BNE, SPARC64_INSN_BPCC_BE + , SPARC64_INSN_BPCC_BG, SPARC64_INSN_BPCC_BLE, SPARC64_INSN_BPCC_BGE, SPARC64_INSN_BPCC_BL + , SPARC64_INSN_BPCC_BGU, SPARC64_INSN_BPCC_BLEU, SPARC64_INSN_BPCC_BCC, SPARC64_INSN_BPCC_BCS + , SPARC64_INSN_BPCC_BPOS, SPARC64_INSN_BPCC_BNEG, SPARC64_INSN_BPCC_BVC, SPARC64_INSN_BPCC_BVS + , SPARC64_INSN_DONE, SPARC64_INSN_RETRY, SPARC64_INSN_FLUSH, SPARC64_INSN_FLUSH_IMM + , SPARC64_INSN_FLUSHW, SPARC64_INSN_IMPDEP1, SPARC64_INSN_IMPDEP2, SPARC64_INSN_MEMBAR + , SPARC64_INSN_MOVA_ICC_ICC, SPARC64_INSN_MOVA_IMM_ICC_ICC, SPARC64_INSN_MOVA_XCC_XCC, SPARC64_INSN_MOVA_IMM_XCC_XCC + , SPARC64_INSN_MOVN_ICC_ICC, SPARC64_INSN_MOVN_IMM_ICC_ICC, SPARC64_INSN_MOVN_XCC_XCC, SPARC64_INSN_MOVN_IMM_XCC_XCC + , SPARC64_INSN_MOVNE_ICC_ICC, SPARC64_INSN_MOVNE_IMM_ICC_ICC, SPARC64_INSN_MOVNE_XCC_XCC, SPARC64_INSN_MOVNE_IMM_XCC_XCC + , SPARC64_INSN_MOVE_ICC_ICC, SPARC64_INSN_MOVE_IMM_ICC_ICC, SPARC64_INSN_MOVE_XCC_XCC, SPARC64_INSN_MOVE_IMM_XCC_XCC + , SPARC64_INSN_MOVG_ICC_ICC, SPARC64_INSN_MOVG_IMM_ICC_ICC, SPARC64_INSN_MOVG_XCC_XCC, SPARC64_INSN_MOVG_IMM_XCC_XCC + , SPARC64_INSN_MOVLE_ICC_ICC, SPARC64_INSN_MOVLE_IMM_ICC_ICC, SPARC64_INSN_MOVLE_XCC_XCC, SPARC64_INSN_MOVLE_IMM_XCC_XCC + , SPARC64_INSN_MOVGE_ICC_ICC, SPARC64_INSN_MOVGE_IMM_ICC_ICC, SPARC64_INSN_MOVGE_XCC_XCC, SPARC64_INSN_MOVGE_IMM_XCC_XCC + , SPARC64_INSN_MOVL_ICC_ICC, SPARC64_INSN_MOVL_IMM_ICC_ICC, SPARC64_INSN_MOVL_XCC_XCC, SPARC64_INSN_MOVL_IMM_XCC_XCC + , SPARC64_INSN_MOVGU_ICC_ICC, SPARC64_INSN_MOVGU_IMM_ICC_ICC, SPARC64_INSN_MOVGU_XCC_XCC, SPARC64_INSN_MOVGU_IMM_XCC_XCC + , SPARC64_INSN_MOVLEU_ICC_ICC, SPARC64_INSN_MOVLEU_IMM_ICC_ICC, SPARC64_INSN_MOVLEU_XCC_XCC, SPARC64_INSN_MOVLEU_IMM_XCC_XCC + , SPARC64_INSN_MOVCC_ICC_ICC, SPARC64_INSN_MOVCC_IMM_ICC_ICC, SPARC64_INSN_MOVCC_XCC_XCC, SPARC64_INSN_MOVCC_IMM_XCC_XCC + , SPARC64_INSN_MOVCS_ICC_ICC, SPARC64_INSN_MOVCS_IMM_ICC_ICC, SPARC64_INSN_MOVCS_XCC_XCC, SPARC64_INSN_MOVCS_IMM_XCC_XCC + , SPARC64_INSN_MOVPOS_ICC_ICC, SPARC64_INSN_MOVPOS_IMM_ICC_ICC, SPARC64_INSN_MOVPOS_XCC_XCC, SPARC64_INSN_MOVPOS_IMM_XCC_XCC + , SPARC64_INSN_MOVNEG_ICC_ICC, SPARC64_INSN_MOVNEG_IMM_ICC_ICC, SPARC64_INSN_MOVNEG_XCC_XCC, SPARC64_INSN_MOVNEG_IMM_XCC_XCC + , SPARC64_INSN_MOVVC_ICC_ICC, SPARC64_INSN_MOVVC_IMM_ICC_ICC, SPARC64_INSN_MOVVC_XCC_XCC, SPARC64_INSN_MOVVC_IMM_XCC_XCC + , SPARC64_INSN_MOVVS_ICC_ICC, SPARC64_INSN_MOVVS_IMM_ICC_ICC, SPARC64_INSN_MOVVS_XCC_XCC, SPARC64_INSN_MOVVS_IMM_XCC_XCC + , SPARC64_INSN_LDSB_REG_REG, SPARC64_INSN_LDSB_REG_IMM, SPARC64_INSN_LDSB_REG_REG_ASI, SPARC64_INSN_LDUB_REG_REG + , SPARC64_INSN_LDUB_REG_IMM, SPARC64_INSN_LDUB_REG_REG_ASI, SPARC64_INSN_LDSH_REG_REG, SPARC64_INSN_LDSH_REG_IMM + , SPARC64_INSN_LDSH_REG_REG_ASI, SPARC64_INSN_LDUH_REG_REG, SPARC64_INSN_LDUH_REG_IMM, SPARC64_INSN_LDUH_REG_REG_ASI + , SPARC64_INSN_LDSW_REG_REG, SPARC64_INSN_LDSW_REG_IMM, SPARC64_INSN_LDSW_REG_REG_ASI, SPARC64_INSN_LDUW_REG_REG + , SPARC64_INSN_LDUW_REG_IMM, SPARC64_INSN_LDUW_REG_REG_ASI, SPARC64_INSN_LDX_REG_REG, SPARC64_INSN_LDX_REG_IMM + , SPARC64_INSN_LDX_REG_REG_ASI, SPARC64_INSN_LDD_REG_REG, SPARC64_INSN_LDD_REG_IMM, SPARC64_INSN_LDD_REG_REG_ASI + , SPARC64_INSN_STB_REG_REG, SPARC64_INSN_STB_REG_IMM, SPARC64_INSN_STB_REG_REG_ASI, SPARC64_INSN_STH_REG_REG + , SPARC64_INSN_STH_REG_IMM, SPARC64_INSN_STH_REG_REG_ASI, SPARC64_INSN_ST_REG_REG, SPARC64_INSN_ST_REG_IMM + , SPARC64_INSN_ST_REG_REG_ASI, SPARC64_INSN_STX_REG_REG, SPARC64_INSN_STX_REG_IMM, SPARC64_INSN_STX_REG_REG_ASI + , SPARC64_INSN_STD_REG_REG, SPARC64_INSN_STD_REG_IMM, SPARC64_INSN_STD_REG_REG_ASI, SPARC64_INSN_FP_LD_REG_REG + , SPARC64_INSN_FP_LD_REG_IMM, SPARC64_INSN_FP_LD_REG_REG_ASI, SPARC64_INSN_SETHI, SPARC64_INSN_ADD + , SPARC64_INSN_ADD_IMM, SPARC64_INSN_SUB, SPARC64_INSN_SUB_IMM, SPARC64_INSN_ADDCC + , SPARC64_INSN_ADDCC_IMM, SPARC64_INSN_SUBCC, SPARC64_INSN_SUBCC_IMM, SPARC64_INSN_ADDC + , SPARC64_INSN_ADDC_IMM, SPARC64_INSN_SUBC, SPARC64_INSN_SUBC_IMM, SPARC64_INSN_ADDCCC + , SPARC64_INSN_ADDCCC_IMM, SPARC64_INSN_SUBCCC, SPARC64_INSN_SUBCCC_IMM, SPARC64_INSN_AND + , SPARC64_INSN_AND_IMM, SPARC64_INSN_ANDCC, SPARC64_INSN_ANDCC_IMM, SPARC64_INSN_OR + , SPARC64_INSN_OR_IMM, SPARC64_INSN_ORCC, SPARC64_INSN_ORCC_IMM, SPARC64_INSN_XOR + , SPARC64_INSN_XOR_IMM, SPARC64_INSN_XORCC, SPARC64_INSN_XORCC_IMM, SPARC64_INSN_ANDN + , SPARC64_INSN_ANDN_IMM, SPARC64_INSN_ANDNCC, SPARC64_INSN_ANDNCC_IMM, SPARC64_INSN_ORN + , SPARC64_INSN_ORN_IMM, SPARC64_INSN_ORNCC, SPARC64_INSN_ORNCC_IMM, SPARC64_INSN_XNOR + , SPARC64_INSN_XNOR_IMM, SPARC64_INSN_XNORCC, SPARC64_INSN_XNORCC_IMM, SPARC64_INSN_SLL + , SPARC64_INSN_SLL_IMM, SPARC64_INSN_SRL, SPARC64_INSN_SRL_IMM, SPARC64_INSN_SRA + , SPARC64_INSN_SRA_IMM, SPARC64_INSN_SMUL, SPARC64_INSN_SMUL_IMM, SPARC64_INSN_SMUL_CC + , SPARC64_INSN_SMUL_CC_IMM, SPARC64_INSN_UMUL, SPARC64_INSN_UMUL_IMM, SPARC64_INSN_UMUL_CC + , SPARC64_INSN_UMUL_CC_IMM, SPARC64_INSN_MULSCC, SPARC64_INSN_SAVE, SPARC64_INSN_SAVE_IMM + , SPARC64_INSN_RESTORE, SPARC64_INSN_RESTORE_IMM, SPARC64_INSN_RETT, SPARC64_INSN_RETT_IMM + , SPARC64_INSN_UNIMP, SPARC64_INSN_CALL, SPARC64_INSN_JMPL, SPARC64_INSN_JMPL_IMM + , SPARC64_INSN_BA, SPARC64_INSN_TA, SPARC64_INSN_TA_IMM, SPARC64_INSN_BN + , SPARC64_INSN_TN, SPARC64_INSN_TN_IMM, SPARC64_INSN_BNE, SPARC64_INSN_TNE + , SPARC64_INSN_TNE_IMM, SPARC64_INSN_BE, SPARC64_INSN_TE, SPARC64_INSN_TE_IMM + , SPARC64_INSN_BG, SPARC64_INSN_TG, SPARC64_INSN_TG_IMM, SPARC64_INSN_BLE + , SPARC64_INSN_TLE, SPARC64_INSN_TLE_IMM, SPARC64_INSN_BGE, SPARC64_INSN_TGE + , SPARC64_INSN_TGE_IMM, SPARC64_INSN_BL, SPARC64_INSN_TL, SPARC64_INSN_TL_IMM + , SPARC64_INSN_BGU, SPARC64_INSN_TGU, SPARC64_INSN_TGU_IMM, SPARC64_INSN_BLEU + , SPARC64_INSN_TLEU, SPARC64_INSN_TLEU_IMM, SPARC64_INSN_BCC, SPARC64_INSN_TCC + , SPARC64_INSN_TCC_IMM, SPARC64_INSN_BCS, SPARC64_INSN_TCS, SPARC64_INSN_TCS_IMM + , SPARC64_INSN_BPOS, SPARC64_INSN_TPOS, SPARC64_INSN_TPOS_IMM, SPARC64_INSN_BNEG + , SPARC64_INSN_TNEG, SPARC64_INSN_TNEG_IMM, SPARC64_INSN_BVC, SPARC64_INSN_TVC + , SPARC64_INSN_TVC_IMM, SPARC64_INSN_BVS, SPARC64_INSN_TVS, SPARC64_INSN_TVS_IMM + , SPARC64_INSN_LDSTUB_REG_REG, SPARC64_INSN_LDSTUB_REG_IMM, SPARC64_INSN_LDSTUB_REG_REG_ASI, SPARC64_INSN_SWAP_REG_REG + , SPARC64_INSN_SWAP_REG_IMM, SPARC64_INSN_SWAP_REG_REG_ASI, SPARC64_INSN_MAX +} SPARC64_INSN_TYPE; + +#if ! WITH_SEM_SWITCH_FULL +#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,fn); +#else +#define SEMFULL(fn) +#endif + +#if ! WITH_SEM_SWITCH_FAST +#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (sparc64,_semf_,fn); +#else +#define SEMFAST(fn) +#endif + +#define SEM(fn) SEMFULL (fn) SEMFAST (fn) + +/* The function version of the before/after handlers is always needed, + so we always want the SEMFULL declaration of them. */ +extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,x_before); +extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,x_after); + +SEM (x_invalid) +SEM (x_after) +SEM (x_before) +SEM (x_cti_chain) +SEM (x_chain) +SEM (x_begin) +SEM (beqz) +SEM (bgez) +SEM (bgtz) +SEM (blez) +SEM (bltz) +SEM (bnez) +SEM (bpcc_ba) +SEM (bpcc_bn) +SEM (bpcc_bne) +SEM (bpcc_be) +SEM (bpcc_bg) +SEM (bpcc_ble) +SEM (bpcc_bge) +SEM (bpcc_bl) +SEM (bpcc_bgu) +SEM (bpcc_bleu) +SEM (bpcc_bcc) +SEM (bpcc_bcs) +SEM (bpcc_bpos) +SEM (bpcc_bneg) +SEM (bpcc_bvc) +SEM (bpcc_bvs) +SEM (done) +SEM (retry) +SEM (flush) +SEM (flush_imm) +SEM (flushw) +SEM (impdep1) +SEM (impdep2) +SEM (membar) +SEM (mova_icc_icc) +SEM (mova_imm_icc_icc) +SEM (mova_xcc_xcc) +SEM (mova_imm_xcc_xcc) +SEM (movn_icc_icc) +SEM (movn_imm_icc_icc) +SEM (movn_xcc_xcc) +SEM (movn_imm_xcc_xcc) +SEM (movne_icc_icc) +SEM (movne_imm_icc_icc) +SEM (movne_xcc_xcc) +SEM (movne_imm_xcc_xcc) +SEM (move_icc_icc) +SEM (move_imm_icc_icc) +SEM (move_xcc_xcc) +SEM (move_imm_xcc_xcc) +SEM (movg_icc_icc) +SEM (movg_imm_icc_icc) +SEM (movg_xcc_xcc) +SEM (movg_imm_xcc_xcc) +SEM (movle_icc_icc) +SEM (movle_imm_icc_icc) +SEM (movle_xcc_xcc) +SEM (movle_imm_xcc_xcc) +SEM (movge_icc_icc) +SEM (movge_imm_icc_icc) +SEM (movge_xcc_xcc) +SEM (movge_imm_xcc_xcc) +SEM (movl_icc_icc) +SEM (movl_imm_icc_icc) +SEM (movl_xcc_xcc) +SEM (movl_imm_xcc_xcc) +SEM (movgu_icc_icc) +SEM (movgu_imm_icc_icc) +SEM (movgu_xcc_xcc) +SEM (movgu_imm_xcc_xcc) +SEM (movleu_icc_icc) +SEM (movleu_imm_icc_icc) +SEM (movleu_xcc_xcc) +SEM (movleu_imm_xcc_xcc) +SEM (movcc_icc_icc) +SEM (movcc_imm_icc_icc) +SEM (movcc_xcc_xcc) +SEM (movcc_imm_xcc_xcc) +SEM (movcs_icc_icc) +SEM (movcs_imm_icc_icc) +SEM (movcs_xcc_xcc) +SEM (movcs_imm_xcc_xcc) +SEM (movpos_icc_icc) +SEM (movpos_imm_icc_icc) +SEM (movpos_xcc_xcc) +SEM (movpos_imm_xcc_xcc) +SEM (movneg_icc_icc) +SEM (movneg_imm_icc_icc) +SEM (movneg_xcc_xcc) +SEM (movneg_imm_xcc_xcc) +SEM (movvc_icc_icc) +SEM (movvc_imm_icc_icc) +SEM (movvc_xcc_xcc) +SEM (movvc_imm_xcc_xcc) +SEM (movvs_icc_icc) +SEM (movvs_imm_icc_icc) +SEM (movvs_xcc_xcc) +SEM (movvs_imm_xcc_xcc) +SEM (ldsb_reg_reg) +SEM (ldsb_reg_imm) +SEM (ldsb_reg_reg_asi) +SEM (ldub_reg_reg) +SEM (ldub_reg_imm) +SEM (ldub_reg_reg_asi) +SEM (ldsh_reg_reg) +SEM (ldsh_reg_imm) +SEM (ldsh_reg_reg_asi) +SEM (lduh_reg_reg) +SEM (lduh_reg_imm) +SEM (lduh_reg_reg_asi) +SEM (ldsw_reg_reg) +SEM (ldsw_reg_imm) +SEM (ldsw_reg_reg_asi) +SEM (lduw_reg_reg) +SEM (lduw_reg_imm) +SEM (lduw_reg_reg_asi) +SEM (ldx_reg_reg) +SEM (ldx_reg_imm) +SEM (ldx_reg_reg_asi) +SEM (ldd_reg_reg) +SEM (ldd_reg_imm) +SEM (ldd_reg_reg_asi) +SEM (stb_reg_reg) +SEM (stb_reg_imm) +SEM (stb_reg_reg_asi) +SEM (sth_reg_reg) +SEM (sth_reg_imm) +SEM (sth_reg_reg_asi) +SEM (st_reg_reg) +SEM (st_reg_imm) +SEM (st_reg_reg_asi) +SEM (stx_reg_reg) +SEM (stx_reg_imm) +SEM (stx_reg_reg_asi) +SEM (std_reg_reg) +SEM (std_reg_imm) +SEM (std_reg_reg_asi) +SEM (fp_ld_reg_reg) +SEM (fp_ld_reg_imm) +SEM (fp_ld_reg_reg_asi) +SEM (sethi) +SEM (add) +SEM (add_imm) +SEM (sub) +SEM (sub_imm) +SEM (addcc) +SEM (addcc_imm) +SEM (subcc) +SEM (subcc_imm) +SEM (addc) +SEM (addc_imm) +SEM (subc) +SEM (subc_imm) +SEM (addccc) +SEM (addccc_imm) +SEM (subccc) +SEM (subccc_imm) +SEM (and) +SEM (and_imm) +SEM (andcc) +SEM (andcc_imm) +SEM (or) +SEM (or_imm) +SEM (orcc) +SEM (orcc_imm) +SEM (xor) +SEM (xor_imm) +SEM (xorcc) +SEM (xorcc_imm) +SEM (andn) +SEM (andn_imm) +SEM (andncc) +SEM (andncc_imm) +SEM (orn) +SEM (orn_imm) +SEM (orncc) +SEM (orncc_imm) +SEM (xnor) +SEM (xnor_imm) +SEM (xnorcc) +SEM (xnorcc_imm) +SEM (sll) +SEM (sll_imm) +SEM (srl) +SEM (srl_imm) +SEM (sra) +SEM (sra_imm) +SEM (smul) +SEM (smul_imm) +SEM (smul_cc) +SEM (smul_cc_imm) +SEM (umul) +SEM (umul_imm) +SEM (umul_cc) +SEM (umul_cc_imm) +SEM (mulscc) +SEM (save) +SEM (save_imm) +SEM (restore) +SEM (restore_imm) +SEM (rett) +SEM (rett_imm) +SEM (unimp) +SEM (call) +SEM (jmpl) +SEM (jmpl_imm) +SEM (ba) +SEM (ta) +SEM (ta_imm) +SEM (bn) +SEM (tn) +SEM (tn_imm) +SEM (bne) +SEM (tne) +SEM (tne_imm) +SEM (be) +SEM (te) +SEM (te_imm) +SEM (bg) +SEM (tg) +SEM (tg_imm) +SEM (ble) +SEM (tle) +SEM (tle_imm) +SEM (bge) +SEM (tge) +SEM (tge_imm) +SEM (bl) +SEM (tl) +SEM (tl_imm) +SEM (bgu) +SEM (tgu) +SEM (tgu_imm) +SEM (bleu) +SEM (tleu) +SEM (tleu_imm) +SEM (bcc) +SEM (tcc) +SEM (tcc_imm) +SEM (bcs) +SEM (tcs) +SEM (tcs_imm) +SEM (bpos) +SEM (tpos) +SEM (tpos_imm) +SEM (bneg) +SEM (tneg) +SEM (tneg_imm) +SEM (bvc) +SEM (tvc) +SEM (tvc_imm) +SEM (bvs) +SEM (tvs) +SEM (tvs_imm) +SEM (ldstub_reg_reg) +SEM (ldstub_reg_imm) +SEM (ldstub_reg_reg_asi) +SEM (swap_reg_reg) +SEM (swap_reg_imm) +SEM (swap_reg_reg_asi) + +#undef SEMFULL +#undef SEMFAST +#undef SEM + +/* Function unit handlers (user written). */ + +extern int sparc64_model_sparc64_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); + +/* Profiling before/after handlers (user written) */ + +extern void sparc64_model_insn_before (SIM_CPU *, int /*first_p*/); +extern void sparc64_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/); + +#endif /* SPARC64_DECODE_H */ diff --git a/sim/sparc/mloop64.in b/sim/sparc/mloop64.in new file mode 100644 index 0000000000..1fd570e23c --- /dev/null +++ b/sim/sparc/mloop64.in @@ -0,0 +1,133 @@ +# Simulator main loop for sparc64. -*- C -*- +# Copyright (C) 1999 Cygnus Solutions. + +# Syntax: +# /bin/sh mainloop.in command +# +# Command is one of: +# +# init +# support +# extract-{simple,scache,pbb} +# {full,fast}-exec-{simple,scache,pbb} +# +# A target need only provide a "full" version of one of simple,scache,pbb. +# If the target wants it can also provide a fast version of same, or if +# the slow (full featured) version is `simple', then the fast version can be +# one of scache/pbb. +# A target can't provide more than this. + +# ??? After a few more ports are done, revisit. +# Will eventually need to machine generate a lot of this. + +case "x$1" in + +xsupport) + +cat <argbuf; + IADDR pc = GET_H_PC (); + USI insn = GETIMEMUSI (current_cpu, pc); + int fast_p = STATE_RUN_FAST_P (CPU_STATE (current_cpu)); + + if (fast_p) + { + const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf); + + @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p); + (*id->sem_full) (current_cpu, sc, insn); + } + else + { + const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf); + const CGEN_INSN *idata = id->idata; + int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc); + int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc); + + @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p); + @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p); + + /* FIXME: call x-before */ + if (ARGBUF_PROFILE_P (abuf)) + PROFILE_COUNT_INSN (current_cpu, pc, id->num); + /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */ + if (PROFILE_MODEL_P (current_cpu) + && ARGBUF_PROFILE_P (abuf)) + @cpu@_model_insn_before (current_cpu, 1 /*first_p*/); + TRACE_INSN_INIT (current_cpu, abuf, 1); + TRACE_INSN (current_cpu, idata, abuf, pc); + + (*id->sem_full) (current_cpu, sc, insn); + + /* FIXME: call x-after */ + if (PROFILE_MODEL_P (current_cpu) + && ARGBUF_PROFILE_P (abuf)) + { + int cycles; + + cycles = (*id->timing->model_fn) (current_cpu, sc); + @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles); + } + TRACE_INSN_FINI (current_cpu, abuf, 1); + } +} + +static INLINE void +do_annul (SIM_CPU *current_cpu) +{ + IADDR npc = GET_H_NPC (); + + /* ??? log profiling data */ + /* ??? anything else */ + + SET_H_PC (npc); + SET_H_NPC (npc + 4); +} + +EOF + +;; + +xinit) + +# Nothing needed. + +;; + +xfull-exec-simple) + +# Inputs: current_cpu, sc, FAST_P +# Outputs: none, instruction is fetched and executed +# Recorded PC is updated after every insn. +# ??? Use of `sc' is a bit of a hack as we don't use the scache. +# We do however use ARGBUF so for consistency with the other engine flavours +# sc is used. + +cat <&2 + exit 1 + ;; + +esac diff --git a/sim/sparc/model64.c b/sim/sparc/model64.c new file mode 100644 index 0000000000..bbbbc169fe --- /dev/null +++ b/sim/sparc/model64.c @@ -0,0 +1,5047 @@ +/* Simulator model support for sparc64. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#define WANT_CPU sparc64 +#define WANT_CPU_SPARC64 + +#include "sim-main.h" + +/* The profiling data is recorded here, but is accessed via the profiling + mechanism. After all, this is information for profiling. */ + +#if WITH_PROFILE_MODEL_P + +/* Model handlers for each insn. */ + +static int +model_sparc64_def_beqz (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bgez (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bgtz (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_blez (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bltz (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bnez (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_ba (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bn (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_BPCC_BA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bne (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_be (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_ble (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bge (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bl (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bgu (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bleu (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bcs (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bpos (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bneg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bvc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpcc_bvs (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_done (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_DONE_VARS /* f-res-18-19 f-op3 f-fcn f-op */ + EXTRACT_IFMT_DONE_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_retry (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_DONE_VARS /* f-res-18-19 f-op3 f-fcn f-op */ + EXTRACT_IFMT_DONE_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_flush (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_FLUSH_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FLUSH_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_flush_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_FLUSH_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FLUSH_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_flushw (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_FLUSHW_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FLUSHW_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_impdep1 (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_IMPDEP1_VARS /* f-impdep19 f-op3 f-impdep5 f-op */ + EXTRACT_IFMT_IMPDEP1_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_impdep2 (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_IMPDEP1_VARS /* f-impdep19 f-op3 f-impdep5 f-op */ + EXTRACT_IFMT_IMPDEP1_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_membar (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MEMBAR_VARS /* f-membarmask f-membar-res12-6 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_MEMBAR_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_mova_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_mova_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_mova_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_mova_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movn_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movn_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movn_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movn_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movne_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movne_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movne_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movne_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_move_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_move_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_move_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_move_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movg_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movg_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movg_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movg_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movle_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movle_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movle_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movle_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movge_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movge_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movge_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movge_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movl_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movl_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movl_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movl_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movgu_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movgu_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movgu_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movgu_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movleu_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movleu_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movleu_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movleu_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movcc_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movcc_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movcc_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movcc_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movcs_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movcs_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movcs_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movcs_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movpos_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movpos_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movpos_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movpos_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movneg_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movneg_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movneg_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movneg_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movvc_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movvc_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movvc_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movvc_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movvs_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movvs_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movvs_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_movvs_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldsb_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldsb_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldsb_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldub_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldub_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldub_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldsh_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldsh_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldsh_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_lduh_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_lduh_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_lduh_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldsw_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldsw_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldsw_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_lduw_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_lduw_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_lduw_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldx_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldx_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldx_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldd_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldd_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldd_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_stb_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_stb_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_stb_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_sth_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_sth_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_sth_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_st_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_st_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_st_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_stx_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_stx_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_stx_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_std_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_std_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_std_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_fp_ld_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_FP_LD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_fp_ld_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_FP_LD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_fp_ld_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_sethi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_SETHI_VARS /* f-hi22 f-op2 f-rd f-op */ + EXTRACT_IFMT_SETHI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_add (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_add_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_sub (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_sub_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_addcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_addcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_subcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_subcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_addc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_addc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_subc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_subc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_addccc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_addccc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_subccc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_subccc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_and (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_and_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_andcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_andcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_or (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_or_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_orcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_orcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_xor (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_xor_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_xorcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_xorcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_andn (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_andn_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_andncc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_andncc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_orn (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_orn_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_orncc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_orncc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_xnor (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_xnor_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_xnorcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_xnorcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_sll (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_sll_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_srl (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_srl_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_sra (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_sra_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_smul (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_smul_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_smul_cc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_smul_cc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_umul (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_umul_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_umul_cc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_umul_cc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_mulscc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_save (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_save_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_restore (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_restore_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_rett (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_FLUSH_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FLUSH_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_rett_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_FLUSH_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FLUSH_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_unimp (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_UNIMP_VARS /* f-imm22 f-op2 f-rd-res f-op */ + EXTRACT_IFMT_UNIMP_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_call (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_CALL_VARS /* f-disp30 f-op */ + IADDR i_disp30; + EXTRACT_IFMT_CALL_CODE + i_disp30 = f_disp30; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_jmpl (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_jmpl_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ba (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ta (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ta_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bn (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_BA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tn (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tn_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bne (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tne (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tne_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_be (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_te (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_te_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ble (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tle (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tle_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bge (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tge (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tge_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bl (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tl (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tl_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bgu (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tgu (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tgu_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bleu (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tleu (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tleu_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bcs (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tcs (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tcs_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bpos (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tpos (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tpos_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bneg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tneg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tneg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bvc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tvc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tvc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_bvs (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tvs (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_tvs_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldstub_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldstub_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_ldstub_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_swap_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_swap_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc64_def_swap_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +/* We assume UNIT_NONE == 0 because the tables don't always terminate + entries with it. */ + +/* Model timing data for `sparc64-def'. */ + +static const INSN_TIMING sparc64_def_timing[] = { + { SPARC64_INSN_X_INVALID, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_X_AFTER, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_X_BEFORE, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_X_CHAIN, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_X_BEGIN, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BEQZ, model_sparc64_def_beqz, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BGEZ, model_sparc64_def_bgez, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BGTZ, model_sparc64_def_bgtz, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BLEZ, model_sparc64_def_blez, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BLTZ, model_sparc64_def_bltz, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BNEZ, model_sparc64_def_bnez, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BA, model_sparc64_def_bpcc_ba, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BN, model_sparc64_def_bpcc_bn, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BNE, model_sparc64_def_bpcc_bne, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BE, model_sparc64_def_bpcc_be, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BG, model_sparc64_def_bpcc_bg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BLE, model_sparc64_def_bpcc_ble, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BGE, model_sparc64_def_bpcc_bge, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BL, model_sparc64_def_bpcc_bl, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BGU, model_sparc64_def_bpcc_bgu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BLEU, model_sparc64_def_bpcc_bleu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BCC, model_sparc64_def_bpcc_bcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BCS, model_sparc64_def_bpcc_bcs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BPOS, model_sparc64_def_bpcc_bpos, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BNEG, model_sparc64_def_bpcc_bneg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BVC, model_sparc64_def_bpcc_bvc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPCC_BVS, model_sparc64_def_bpcc_bvs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_DONE, model_sparc64_def_done, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_RETRY, model_sparc64_def_retry, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_FLUSH, model_sparc64_def_flush, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_FLUSH_IMM, model_sparc64_def_flush_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_FLUSHW, model_sparc64_def_flushw, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_IMPDEP1, model_sparc64_def_impdep1, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_IMPDEP2, model_sparc64_def_impdep2, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MEMBAR, model_sparc64_def_membar, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVA_ICC_ICC, model_sparc64_def_mova_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVA_IMM_ICC_ICC, model_sparc64_def_mova_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVA_XCC_XCC, model_sparc64_def_mova_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVA_IMM_XCC_XCC, model_sparc64_def_mova_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVN_ICC_ICC, model_sparc64_def_movn_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVN_IMM_ICC_ICC, model_sparc64_def_movn_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVN_XCC_XCC, model_sparc64_def_movn_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVN_IMM_XCC_XCC, model_sparc64_def_movn_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVNE_ICC_ICC, model_sparc64_def_movne_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVNE_IMM_ICC_ICC, model_sparc64_def_movne_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVNE_XCC_XCC, model_sparc64_def_movne_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVNE_IMM_XCC_XCC, model_sparc64_def_movne_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVE_ICC_ICC, model_sparc64_def_move_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVE_IMM_ICC_ICC, model_sparc64_def_move_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVE_XCC_XCC, model_sparc64_def_move_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVE_IMM_XCC_XCC, model_sparc64_def_move_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVG_ICC_ICC, model_sparc64_def_movg_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVG_IMM_ICC_ICC, model_sparc64_def_movg_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVG_XCC_XCC, model_sparc64_def_movg_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVG_IMM_XCC_XCC, model_sparc64_def_movg_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVLE_ICC_ICC, model_sparc64_def_movle_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVLE_IMM_ICC_ICC, model_sparc64_def_movle_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVLE_XCC_XCC, model_sparc64_def_movle_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVLE_IMM_XCC_XCC, model_sparc64_def_movle_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVGE_ICC_ICC, model_sparc64_def_movge_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVGE_IMM_ICC_ICC, model_sparc64_def_movge_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVGE_XCC_XCC, model_sparc64_def_movge_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVGE_IMM_XCC_XCC, model_sparc64_def_movge_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVL_ICC_ICC, model_sparc64_def_movl_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVL_IMM_ICC_ICC, model_sparc64_def_movl_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVL_XCC_XCC, model_sparc64_def_movl_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVL_IMM_XCC_XCC, model_sparc64_def_movl_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVGU_ICC_ICC, model_sparc64_def_movgu_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVGU_IMM_ICC_ICC, model_sparc64_def_movgu_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVGU_XCC_XCC, model_sparc64_def_movgu_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVGU_IMM_XCC_XCC, model_sparc64_def_movgu_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVLEU_ICC_ICC, model_sparc64_def_movleu_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVLEU_IMM_ICC_ICC, model_sparc64_def_movleu_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVLEU_XCC_XCC, model_sparc64_def_movleu_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVLEU_IMM_XCC_XCC, model_sparc64_def_movleu_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVCC_ICC_ICC, model_sparc64_def_movcc_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVCC_IMM_ICC_ICC, model_sparc64_def_movcc_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVCC_XCC_XCC, model_sparc64_def_movcc_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVCC_IMM_XCC_XCC, model_sparc64_def_movcc_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVCS_ICC_ICC, model_sparc64_def_movcs_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVCS_IMM_ICC_ICC, model_sparc64_def_movcs_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVCS_XCC_XCC, model_sparc64_def_movcs_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVCS_IMM_XCC_XCC, model_sparc64_def_movcs_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVPOS_ICC_ICC, model_sparc64_def_movpos_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVPOS_IMM_ICC_ICC, model_sparc64_def_movpos_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVPOS_XCC_XCC, model_sparc64_def_movpos_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVPOS_IMM_XCC_XCC, model_sparc64_def_movpos_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVNEG_ICC_ICC, model_sparc64_def_movneg_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVNEG_IMM_ICC_ICC, model_sparc64_def_movneg_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVNEG_XCC_XCC, model_sparc64_def_movneg_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVNEG_IMM_XCC_XCC, model_sparc64_def_movneg_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVVC_ICC_ICC, model_sparc64_def_movvc_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVVC_IMM_ICC_ICC, model_sparc64_def_movvc_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVVC_XCC_XCC, model_sparc64_def_movvc_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVVC_IMM_XCC_XCC, model_sparc64_def_movvc_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVVS_ICC_ICC, model_sparc64_def_movvs_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVVS_IMM_ICC_ICC, model_sparc64_def_movvs_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVVS_XCC_XCC, model_sparc64_def_movvs_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MOVVS_IMM_XCC_XCC, model_sparc64_def_movvs_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSB_REG_REG, model_sparc64_def_ldsb_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSB_REG_IMM, model_sparc64_def_ldsb_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSB_REG_REG_ASI, model_sparc64_def_ldsb_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDUB_REG_REG, model_sparc64_def_ldub_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDUB_REG_IMM, model_sparc64_def_ldub_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDUB_REG_REG_ASI, model_sparc64_def_ldub_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSH_REG_REG, model_sparc64_def_ldsh_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSH_REG_IMM, model_sparc64_def_ldsh_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSH_REG_REG_ASI, model_sparc64_def_ldsh_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDUH_REG_REG, model_sparc64_def_lduh_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDUH_REG_IMM, model_sparc64_def_lduh_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDUH_REG_REG_ASI, model_sparc64_def_lduh_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSW_REG_REG, model_sparc64_def_ldsw_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSW_REG_IMM, model_sparc64_def_ldsw_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSW_REG_REG_ASI, model_sparc64_def_ldsw_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDUW_REG_REG, model_sparc64_def_lduw_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDUW_REG_IMM, model_sparc64_def_lduw_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDUW_REG_REG_ASI, model_sparc64_def_lduw_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDX_REG_REG, model_sparc64_def_ldx_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDX_REG_IMM, model_sparc64_def_ldx_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDX_REG_REG_ASI, model_sparc64_def_ldx_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDD_REG_REG, model_sparc64_def_ldd_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDD_REG_IMM, model_sparc64_def_ldd_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDD_REG_REG_ASI, model_sparc64_def_ldd_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STB_REG_REG, model_sparc64_def_stb_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STB_REG_IMM, model_sparc64_def_stb_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STB_REG_REG_ASI, model_sparc64_def_stb_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STH_REG_REG, model_sparc64_def_sth_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STH_REG_IMM, model_sparc64_def_sth_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STH_REG_REG_ASI, model_sparc64_def_sth_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ST_REG_REG, model_sparc64_def_st_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ST_REG_IMM, model_sparc64_def_st_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ST_REG_REG_ASI, model_sparc64_def_st_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STX_REG_REG, model_sparc64_def_stx_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STX_REG_IMM, model_sparc64_def_stx_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STX_REG_REG_ASI, model_sparc64_def_stx_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STD_REG_REG, model_sparc64_def_std_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STD_REG_IMM, model_sparc64_def_std_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_STD_REG_REG_ASI, model_sparc64_def_std_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_FP_LD_REG_REG, model_sparc64_def_fp_ld_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_FP_LD_REG_IMM, model_sparc64_def_fp_ld_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_FP_LD_REG_REG_ASI, model_sparc64_def_fp_ld_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SETHI, model_sparc64_def_sethi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ADD, model_sparc64_def_add, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ADD_IMM, model_sparc64_def_add_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SUB, model_sparc64_def_sub, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SUB_IMM, model_sparc64_def_sub_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ADDCC, model_sparc64_def_addcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ADDCC_IMM, model_sparc64_def_addcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SUBCC, model_sparc64_def_subcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SUBCC_IMM, model_sparc64_def_subcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ADDC, model_sparc64_def_addc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ADDC_IMM, model_sparc64_def_addc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SUBC, model_sparc64_def_subc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SUBC_IMM, model_sparc64_def_subc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ADDCCC, model_sparc64_def_addccc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ADDCCC_IMM, model_sparc64_def_addccc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SUBCCC, model_sparc64_def_subccc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SUBCCC_IMM, model_sparc64_def_subccc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_AND, model_sparc64_def_and, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_AND_IMM, model_sparc64_def_and_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ANDCC, model_sparc64_def_andcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ANDCC_IMM, model_sparc64_def_andcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_OR, model_sparc64_def_or, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_OR_IMM, model_sparc64_def_or_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ORCC, model_sparc64_def_orcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ORCC_IMM, model_sparc64_def_orcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_XOR, model_sparc64_def_xor, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_XOR_IMM, model_sparc64_def_xor_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_XORCC, model_sparc64_def_xorcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_XORCC_IMM, model_sparc64_def_xorcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ANDN, model_sparc64_def_andn, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ANDN_IMM, model_sparc64_def_andn_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ANDNCC, model_sparc64_def_andncc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ANDNCC_IMM, model_sparc64_def_andncc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ORN, model_sparc64_def_orn, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ORN_IMM, model_sparc64_def_orn_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ORNCC, model_sparc64_def_orncc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_ORNCC_IMM, model_sparc64_def_orncc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_XNOR, model_sparc64_def_xnor, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_XNOR_IMM, model_sparc64_def_xnor_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_XNORCC, model_sparc64_def_xnorcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_XNORCC_IMM, model_sparc64_def_xnorcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SLL, model_sparc64_def_sll, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SLL_IMM, model_sparc64_def_sll_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SRL, model_sparc64_def_srl, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SRL_IMM, model_sparc64_def_srl_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SRA, model_sparc64_def_sra, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SRA_IMM, model_sparc64_def_sra_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SMUL, model_sparc64_def_smul, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SMUL_IMM, model_sparc64_def_smul_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SMUL_CC, model_sparc64_def_smul_cc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SMUL_CC_IMM, model_sparc64_def_smul_cc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_UMUL, model_sparc64_def_umul, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_UMUL_IMM, model_sparc64_def_umul_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_UMUL_CC, model_sparc64_def_umul_cc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_UMUL_CC_IMM, model_sparc64_def_umul_cc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_MULSCC, model_sparc64_def_mulscc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SAVE, model_sparc64_def_save, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SAVE_IMM, model_sparc64_def_save_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_RESTORE, model_sparc64_def_restore, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_RESTORE_IMM, model_sparc64_def_restore_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_RETT, model_sparc64_def_rett, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_RETT_IMM, model_sparc64_def_rett_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_UNIMP, model_sparc64_def_unimp, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_CALL, model_sparc64_def_call, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_JMPL, model_sparc64_def_jmpl, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_JMPL_IMM, model_sparc64_def_jmpl_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BA, model_sparc64_def_ba, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TA, model_sparc64_def_ta, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TA_IMM, model_sparc64_def_ta_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BN, model_sparc64_def_bn, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TN, model_sparc64_def_tn, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TN_IMM, model_sparc64_def_tn_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BNE, model_sparc64_def_bne, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TNE, model_sparc64_def_tne, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TNE_IMM, model_sparc64_def_tne_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BE, model_sparc64_def_be, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TE, model_sparc64_def_te, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TE_IMM, model_sparc64_def_te_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BG, model_sparc64_def_bg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TG, model_sparc64_def_tg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TG_IMM, model_sparc64_def_tg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BLE, model_sparc64_def_ble, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TLE, model_sparc64_def_tle, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TLE_IMM, model_sparc64_def_tle_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BGE, model_sparc64_def_bge, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TGE, model_sparc64_def_tge, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TGE_IMM, model_sparc64_def_tge_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BL, model_sparc64_def_bl, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TL, model_sparc64_def_tl, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TL_IMM, model_sparc64_def_tl_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BGU, model_sparc64_def_bgu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TGU, model_sparc64_def_tgu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TGU_IMM, model_sparc64_def_tgu_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BLEU, model_sparc64_def_bleu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TLEU, model_sparc64_def_tleu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TLEU_IMM, model_sparc64_def_tleu_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BCC, model_sparc64_def_bcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TCC, model_sparc64_def_tcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TCC_IMM, model_sparc64_def_tcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BCS, model_sparc64_def_bcs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TCS, model_sparc64_def_tcs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TCS_IMM, model_sparc64_def_tcs_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BPOS, model_sparc64_def_bpos, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TPOS, model_sparc64_def_tpos, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TPOS_IMM, model_sparc64_def_tpos_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BNEG, model_sparc64_def_bneg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TNEG, model_sparc64_def_tneg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TNEG_IMM, model_sparc64_def_tneg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BVC, model_sparc64_def_bvc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TVC, model_sparc64_def_tvc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TVC_IMM, model_sparc64_def_tvc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_BVS, model_sparc64_def_bvs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TVS, model_sparc64_def_tvs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_TVS_IMM, model_sparc64_def_tvs_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSTUB_REG_REG, model_sparc64_def_ldstub_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSTUB_REG_IMM, model_sparc64_def_ldstub_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_LDSTUB_REG_REG_ASI, model_sparc64_def_ldstub_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SWAP_REG_REG, model_sparc64_def_swap_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SWAP_REG_IMM, model_sparc64_def_swap_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, + { SPARC64_INSN_SWAP_REG_REG_ASI, model_sparc64_def_swap_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, +}; + +#endif /* WITH_PROFILE_MODEL_P */ + +static void +sparc64_def_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_SPARC64_DEF_DATA)); +} + +#if WITH_PROFILE_MODEL_P +#define TIMING_DATA(td) td +#else +#define TIMING_DATA(td) 0 +#endif + +static const MODEL sparc_v9_models[] = +{ + { "sparc64-def", & sparc_v9_mach, MODEL_SPARC64_DEF, TIMING_DATA (& sparc64_def_timing[0]), sparc64_def_model_init }, + { 0 } +}; + +/* The properties of this cpu's implementation. */ + +static const MACH_IMP_PROPERTIES sparc64_imp_properties = +{ + sizeof (SIM_CPU), +#if WITH_SCACHE + sizeof (SCACHE) +#else + 0 +#endif +}; + + +static void +sparc64_prepare_run (SIM_CPU *cpu) +{ + if (CPU_IDESC (cpu) == NULL) + sparc64_init_idesc_table (cpu); +} + +static const CGEN_INSN * +sparc64_get_idata (SIM_CPU *cpu, int inum) +{ + return CPU_IDESC (cpu) [inum].idata; +} + +static void +sparc_v9_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = sparc64_fetch_register; + CPU_REG_STORE (cpu) = sparc64_store_register; + CPU_PC_FETCH (cpu) = sparc64_h_pc_get; + CPU_PC_STORE (cpu) = sparc64_h_pc_set; + CPU_GET_IDATA (cpu) = sparc64_get_idata; + CPU_MAX_INSNS (cpu) = SPARC64_INSN_MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = sparc64_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = sparc64_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = sparc64_engine_run_full; +#endif +} + +const MACH sparc_v9_mach = +{ + "sparc-v9", "sparc_v9", + 64, 64, & sparc_v9_models[0], & sparc64_imp_properties, + sparc_v9_init_cpu, + sparc64_prepare_run +}; + diff --git a/sim/sparc/regs64.h b/sim/sparc/regs64.h new file mode 100644 index 0000000000..f84d068c10 --- /dev/null +++ b/sim/sparc/regs64.h @@ -0,0 +1,74 @@ +/* sparc64 register definitions + Copyright (C) 1999 Cygnus Solutions. */ + +#ifndef REG64_H +#define REG64_H + +/* The PSR is a hodge-podge of various things. + ??? The final organization of this is wip. */ + +extern USI sparc32_get_h_psr_handler (SIM_CPU *); +extern void sparc32_set_h_psr_handler (SIM_CPU *, USI); +#define GET_H_PSR() sparc32_get_h_psr_handler (current_cpu) +#define SET_H_PSR(val) sparc32_set_h_psr_handler (current_cpu, (val)) + +/* The y reg is a virtual reg as it's actually one of the asr regs. + ??? To be replaced in time with get/set specs. */ +#if 0 +#define sparc32_h_y_get(cpu) (CPU_CGEN_HW (cpu)->h_asr[0]) +#define sparc32_h_y_set(cpu,val) (CPU_CGEN_HW (cpu)->h_asr[0] = (val)) +#endif +#define GET_H_Y() (CPU (h_asr) [0]) +#define SET_H_Y(newval) do { CPU (h_asr) [0] = (newval); } while (0) + +/* The Trap Base Register. */ +#define GET_H_TBR() CPU (h_tbr) +#define SET_H_TBR(newval) \ + do { \ + CPU (h_tbr) = (CPU (h_tbr) & 0xff0) | ((newval) & 0xfffff000); \ + } while (0) + +/* sparc32 register window stuff. */ + +/* Handle gets/sets of h-cwp. + This handles swapping out the current set of window registers + and swapping in the new. How the "swapping" is done depends on the + register window implementation of the day. */ +void sparc32_set_h_cwp_handler (SIM_CPU *, int); +#define GET_H_CWP() CPU (h_cwp) +#define SET_H_CWP(newval) sparc32_set_h_cwp_handler (current_cpu, (newval)) + +/* WIM accessors. */ +/* ??? Yes, mask computation assumes nwindows < 32. */ +#define GET_H_WIM() (CPU (h_wim) & ((1 << GET_NWINDOWS ()) - 1)) +#define SET_H_WIM(newval) (CPU (h_wim) = (newval)) + +/* Return non-zero if window WIN is valid in WIM. */ +#define WINDOW_VALID_P(win, wim) (((wim) & (1 << (win))) == 0) + +void sparc32_alloc_regwins (SIM_CPU *, int); +void sparc32_free_regwins (SIM_CPU *); +void sparc32_swapout_regwin (SIM_CPU *, int); +void sparc32_swapin_regwin (SIM_CPU *, int); + +void sparc32_load_regwin (SIM_CPU *, IADDR pc_, int win_); +void sparc32_flush_regwin (SIM_CPU *, IADDR pc_, int win_, int no_errors_p_); +void sparc32_flush_regwins (SIM_CPU *, IADDR pc_, int no_errors_p_); + +void sparc32_save_regwin (SIM_CPU *); +void sparc32_restore_regwin (SIM_CPU *); + +/* Integer register access macros. + Provides an interface between the cpu description and the register window + implementation of the day. To be solidified in time. */ +#define GET_H_GR(r) (current_cpu->current_regs[r]) + +/* ??? The r != 0 test may not be necessary as sufficient numbers of dni + entries can prevent this from occuring (I think). Even then though doing + this makes things more robust, and a lot of dni's would be needed. + ??? The other way to handle %g0 is to always reset it for each insn + [perhaps optimized to only do so when necessary]. */ +#define SET_H_GR(r, val) \ + ((r) != 0 ? (current_cpu->current_regs[r] = (val)) : 0) + +#endif /* REG64_H */ diff --git a/sim/sparc/sem64.c b/sim/sparc/sem64.c new file mode 100644 index 0000000000..17bec6f96c --- /dev/null +++ b/sim/sparc/sem64.c @@ -0,0 +1,7569 @@ +/* Simulator instruction semantics for sparc64. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#define WANT_CPU sparc64 +#define WANT_CPU_SPARC64 + +#include "sim-main.h" +#include "cgen-mem.h" +#include "cgen-ops.h" + +#undef GET_ATTR +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) + +/* x-invalid: --invalid-- */ + +SEM_STATUS +SEM_FN_NAME (sparc64,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE + /* Update the recorded pc in the cpu state struct. */ + SET_H_PC (pc); +#endif + sim_engine_invalid_insn (current_cpu, pc); + sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n"); + /* NOTREACHED */ + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* x-after: --after-- */ + +SEM_STATUS +SEM_FN_NAME (sparc64,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE_PBB_SPARC64 + sparc64_pbb_after (current_cpu, sem_arg); +#endif + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* x-before: --before-- */ + +SEM_STATUS +SEM_FN_NAME (sparc64,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE_PBB_SPARC64 + sparc64_pbb_before (current_cpu, sem_arg); +#endif + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* x-cti-chain: --cti-chain-- */ + +SEM_STATUS +SEM_FN_NAME (sparc64,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE_PBB_SPARC64 +#ifdef DEFINE_SWITCH + vpc = sparc64_pbb_cti_chain (current_cpu, sem_arg, + pbb_br_npc_ptr, pbb_br_npc); + BREAK (sem); +#else + /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ + vpc = sparc64_pbb_cti_chain (current_cpu, sem_arg, + CPU_PBB_BR_NPC_PTR (current_cpu), + CPU_PBB_BR_NPC (current_cpu)); +#endif +#endif + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* x-chain: --chain-- */ + +SEM_STATUS +SEM_FN_NAME (sparc64,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE_PBB_SPARC64 + vpc = sparc64_pbb_chain (current_cpu, sem_arg); +#ifdef DEFINE_SWITCH + BREAK (sem); +#endif +#endif + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* x-begin: --begin-- */ + +SEM_STATUS +SEM_FN_NAME (sparc64,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE_PBB_SPARC64 +#ifdef DEFINE_SWITCH + /* In the switch case FAST_P is a constant, allowing several optimizations + in any called inline functions. */ + vpc = sparc64_pbb_begin (current_cpu, FAST_P); +#else + vpc = sparc64_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); +#endif +#endif + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* beqz: beqz$a$p $rs1,$disp16 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + +do { +if (EQSI (GET_H_GR (f_rs1), 0)) { + { + USI opval = i_disp16; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bgez: bgez$a$p $rs1,$disp16 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + +do { +if (GESI (GET_H_GR (f_rs1), 0)) { + { + USI opval = i_disp16; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bgtz: bgtz$a$p $rs1,$disp16 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + +do { +if (GTSI (GET_H_GR (f_rs1), 0)) { + { + USI opval = i_disp16; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* blez: blez$a$p $rs1,$disp16 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + +do { +if (LESI (GET_H_GR (f_rs1), 0)) { + { + USI opval = i_disp16; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bltz: bltz$a$p $rs1,$disp16 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + +do { +if (LTSI (GET_H_GR (f_rs1), 0)) { + { + USI opval = i_disp16; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bnez: bnez$a$p $rs1,$disp16 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ + IADDR i_disp16; + EXTRACT_IFMT_BEQZ_CODE + i_disp16 = f_disp16; + +do { +if (NESI (GET_H_GR (f_rs1), 0)) { + { + USI opval = i_disp16; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-ba: ba$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_ba) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +do { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} while (0); +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bn: bn$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_BPCC_BA_CODE + +do { +do { +do { } while (0); /*nop*/ +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bne: bne$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_xcc_z))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-be: be$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_be) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_xcc_z)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bg: bg$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v))))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-ble: ble$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bge: bge$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bl: bl$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (XORBI (CPU (h_xcc_n), CPU (h_xcc_v))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bgu: bgu$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (ORBI (CPU (h_xcc_c), CPU (h_xcc_z)))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bleu: bleu$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (ORBI (CPU (h_xcc_c), CPU (h_xcc_z))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bcc: bcc$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_xcc_c))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bcs: bcs$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_xcc_c)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bpos: bpos$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bpos) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_xcc_n))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bneg: bneg$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bneg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_xcc_n)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bvc: bvc$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bvc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_xcc_v))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpcc-bvs: bvs$a$p %xcc,$disp19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpcc_bvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BPCC_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_xcc_v)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* done: done */ + +SEM_STATUS +SEM_FN_NAME (sparc64,done) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_DONE_VARS /* f-res-18-19 f-op3 f-fcn f-op */ + EXTRACT_IFMT_DONE_CODE + +sparc64_done (current_cpu, pc); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* retry: done */ + +SEM_STATUS +SEM_FN_NAME (sparc64,retry) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_DONE_VARS /* f-res-18-19 f-op3 f-fcn f-op */ + EXTRACT_IFMT_DONE_CODE + +sparc64_retry (current_cpu, pc); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* flush: flush */ + +SEM_STATUS +SEM_FN_NAME (sparc64,flush) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_FLUSH_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FLUSH_CODE + +sparc64_flush (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* flush-imm: flush */ + +SEM_STATUS +SEM_FN_NAME (sparc64,flush_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_FLUSH_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FLUSH_IMM_CODE + +sparc64_flush (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* flushw: flushw */ + +SEM_STATUS +SEM_FN_NAME (sparc64,flushw) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_FLUSHW_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FLUSHW_CODE + +sparc64_flushw (current_cpu, pc); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* impdep1: impdep1 $impdep5,$impdep19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,impdep1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_IMPDEP1_VARS /* f-impdep19 f-op3 f-impdep5 f-op */ + EXTRACT_IFMT_IMPDEP1_CODE + +sparc64_impdep1 (current_cpu, pc, f_impdep5, f_impdep19); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* impdep2: impdep2 $impdep5,$impdep19 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,impdep2) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_IMPDEP1_VARS /* f-impdep19 f-op3 f-impdep5 f-op */ + EXTRACT_IFMT_IMPDEP1_CODE + +sparc64_impdep2 (current_cpu, pc, f_impdep5, f_impdep19); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* membar: member $membarmask */ + +SEM_STATUS +SEM_FN_NAME (sparc64,membar) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MEMBAR_VARS /* f-membarmask f-membar-res12-6 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_MEMBAR_CODE + +sparc64_membar (current_cpu, pc, f_membarmask); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* mova-icc-icc: mova-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,mova_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* mova-imm-icc-icc: mova-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,mova_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* mova-xcc-xcc: mova-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,mova_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* mova-imm-xcc-xcc: mova-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,mova_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movn-icc-icc: movn-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movn_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +do { } while (0); /*nop*/ + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movn-imm-icc-icc: movn-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movn_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +do { } while (0); /*nop*/ + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movn-xcc-xcc: movn-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movn_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +do { } while (0); /*nop*/ + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movn-imm-xcc-xcc: movn-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movn_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +do { } while (0); /*nop*/ + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movne-icc-icc: movne-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movne_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (CPU (h_icc_z))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movne-imm-icc-icc: movne-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movne_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (CPU (h_icc_z))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movne-xcc-xcc: movne-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movne_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (CPU (h_xcc_z))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movne-imm-xcc-xcc: movne-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movne_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (CPU (h_xcc_z))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* move-icc-icc: move-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,move_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (CPU (h_icc_z)) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* move-imm-icc-icc: move-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,move_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (CPU (h_icc_z)) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* move-xcc-xcc: move-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,move_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (CPU (h_xcc_z)) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* move-imm-xcc-xcc: move-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,move_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (CPU (h_xcc_z)) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movg-icc-icc: movg-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movg_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movg-imm-icc-icc: movg-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movg_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movg-xcc-xcc: movg-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movg_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v))))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movg-imm-xcc-xcc: movg-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movg_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v))))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movle-icc-icc: movle-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movle_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movle-imm-icc-icc: movle-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movle_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movle-xcc-xcc: movle-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movle_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movle-imm-xcc-xcc: movle-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movle_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movge-icc-icc: movge-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movge_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movge-imm-icc-icc: movge-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movge_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movge-xcc-xcc: movge-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movge_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movge-imm-xcc-xcc: movge-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movge_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movl-icc-icc: movl-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movl_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movl-imm-icc-icc: movl-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movl_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movl-xcc-xcc: movl-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movl_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (XORBI (CPU (h_xcc_n), CPU (h_xcc_v))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movl-imm-xcc-xcc: movl-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movl_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (XORBI (CPU (h_xcc_n), CPU (h_xcc_v))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movgu-icc-icc: movgu-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movgu_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movgu-imm-icc-icc: movgu-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movgu_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movgu-xcc-xcc: movgu-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movgu_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (ORBI (CPU (h_xcc_c), CPU (h_xcc_z)))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movgu-imm-xcc-xcc: movgu-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movgu_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (ORBI (CPU (h_xcc_c), CPU (h_xcc_z)))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movleu-icc-icc: movleu-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movleu_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movleu-imm-icc-icc: movleu-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movleu_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movleu-xcc-xcc: movleu-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movleu_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (ORBI (CPU (h_xcc_c), CPU (h_xcc_z))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movleu-imm-xcc-xcc: movleu-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movleu_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (ORBI (CPU (h_xcc_c), CPU (h_xcc_z))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movcc-icc-icc: movcc-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movcc_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (CPU (h_icc_c))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movcc-imm-icc-icc: movcc-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movcc_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (CPU (h_icc_c))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movcc-xcc-xcc: movcc-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movcc_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (CPU (h_xcc_c))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movcc-imm-xcc-xcc: movcc-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movcc_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (CPU (h_xcc_c))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movcs-icc-icc: movcs-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movcs_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (CPU (h_icc_c)) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movcs-imm-icc-icc: movcs-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movcs_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (CPU (h_icc_c)) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movcs-xcc-xcc: movcs-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movcs_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (CPU (h_xcc_c)) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movcs-imm-xcc-xcc: movcs-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movcs_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (CPU (h_xcc_c)) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movpos-icc-icc: movpos-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movpos_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (CPU (h_icc_n))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movpos-imm-icc-icc: movpos-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movpos_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (CPU (h_icc_n))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movpos-xcc-xcc: movpos-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movpos_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (CPU (h_xcc_n))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movpos-imm-xcc-xcc: movpos-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movpos_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (CPU (h_xcc_n))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movneg-icc-icc: movneg-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movneg_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (CPU (h_icc_n)) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movneg-imm-icc-icc: movneg-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movneg_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (CPU (h_icc_n)) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movneg-xcc-xcc: movneg-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movneg_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (CPU (h_xcc_n)) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movneg-imm-xcc-xcc: movneg-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movneg_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (CPU (h_xcc_n)) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movvc-icc-icc: movvc-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movvc_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (CPU (h_icc_v))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movvc-imm-icc-icc: movvc-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movvc_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (CPU (h_icc_v))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movvc-xcc-xcc: movvc-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movvc_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (NOTBI (CPU (h_xcc_v))) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movvc-imm-xcc-xcc: movvc-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movvc_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (NOTBI (CPU (h_xcc_v))) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movvs-icc-icc: movvs-icc %icc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movvs_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (CPU (h_icc_v)) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movvs-imm-icc-icc: movvs-imm-icc %icc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movvs_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (CPU (h_icc_v)) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movvs-xcc-xcc: movvs-xcc %xcc,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movvs_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_ICC_ICC_CODE + +if (CPU (h_xcc_v)) { + { + SI opval = GET_H_GR (f_rs2); + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* movvs-imm-xcc-xcc: movvs-imm-xcc %xcc,$simm11,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,movvs_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ + EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE + +if (CPU (h_xcc_v)) { + { + SI opval = f_simm11; + SET_H_GR (f_rd, opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} + + abuf->written = written; + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsb-reg+reg: ldsb [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldsb_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsb-reg+imm: ldsb [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldsb_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsb-reg+reg/asi: ldsb [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldsb_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldub-reg+reg: ldub [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldub_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldub-reg+imm: ldub [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldub_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldub-reg+reg/asi: ldub [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldub_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsh-reg+reg: ldsh [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldsh_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsh-reg+imm: ldsh [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldsh_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsh-reg+reg/asi: ldsh [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldsh_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduh-reg+reg: lduh [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,lduh_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduh-reg+imm: lduh [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,lduh_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduh-reg+reg/asi: lduh [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,lduh_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsw-reg+reg: ldsw [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldsw_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsw-reg+imm: ldsw [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldsw_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsw-reg+reg/asi: ldsw [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldsw_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduw-reg+reg: lduw [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,lduw_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduw-reg+imm: lduw [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,lduw_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduw-reg+reg/asi: lduw [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,lduw_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldx-reg+reg: ldx [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldx_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + DI opval = GETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldx-reg+imm: ldx [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldx_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + DI opval = GETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldx-reg+reg/asi: ldx [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldx_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + + { + DI opval = GETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldd-reg+reg: ldd [$rs1+$rs2],$rdd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldd_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_CODE + +do { + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); + } + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4))); + SET_H_GR (((f_rd) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldd-reg+imm: ldd [$rs1+$simm13],$rdd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldd_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_IMM_CODE + +do { + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); + } + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDHI (f_simm13, 4))); + SET_H_GR (((f_rd) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldd-reg+reg/asi: ldd [$rs1+$rs2]$asi,$rdd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldd_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_ASI_CODE + +do { + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); + } + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4))); + SET_H_GR (((f_rd) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* stb-reg+reg: stb $rd,[$rs1+$rs2] */ + +SEM_STATUS +SEM_FN_NAME (sparc64,stb_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + QI opval = GET_H_GR (f_rd); + SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* stb-reg+imm: stb $rd,[$rs1+$simm13] */ + +SEM_STATUS +SEM_FN_NAME (sparc64,stb_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + QI opval = GET_H_GR (f_rd); + SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* stb-reg+reg/asi: stb $rd,[$rs1+$rs2]$asi */ + +SEM_STATUS +SEM_FN_NAME (sparc64,stb_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + + { + QI opval = GET_H_GR (f_rd); + SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sth-reg+reg: sth $rd,[$rs1+$rs2] */ + +SEM_STATUS +SEM_FN_NAME (sparc64,sth_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + HI opval = GET_H_GR (f_rd); + SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sth-reg+imm: sth $rd,[$rs1+$simm13] */ + +SEM_STATUS +SEM_FN_NAME (sparc64,sth_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + HI opval = GET_H_GR (f_rd); + SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sth-reg+reg/asi: sth $rd,[$rs1+$rs2]$asi */ + +SEM_STATUS +SEM_FN_NAME (sparc64,sth_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + + { + HI opval = GET_H_GR (f_rd); + SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* st-reg+reg: st $rd,[$rs1+$rs2] */ + +SEM_STATUS +SEM_FN_NAME (sparc64,st_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* st-reg+imm: st $rd,[$rs1+$simm13] */ + +SEM_STATUS +SEM_FN_NAME (sparc64,st_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* st-reg+reg/asi: st $rd,[$rs1+$rs2]$asi */ + +SEM_STATUS +SEM_FN_NAME (sparc64,st_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* stx-reg+reg: stx $rd,[$rs1+$rs2] */ + +SEM_STATUS +SEM_FN_NAME (sparc64,stx_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + DI opval = GET_H_GR (f_rd); + SETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* stx-reg+imm: stx $rd,[$rs1+$simm13] */ + +SEM_STATUS +SEM_FN_NAME (sparc64,stx_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + DI opval = GET_H_GR (f_rd); + SETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* stx-reg+reg/asi: stx $rd,[$rs1+$rs2]$asi */ + +SEM_STATUS +SEM_FN_NAME (sparc64,stx_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + + { + DI opval = GET_H_GR (f_rd); + SETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* std-reg+reg: std $rdd,[$rs1+$rs2] */ + +SEM_STATUS +SEM_FN_NAME (sparc64,std_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_CODE + +do { + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = GET_H_GR (((f_rd) + (1))); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* std-reg+imm: std $rdd,[$rs1+$simm13] */ + +SEM_STATUS +SEM_FN_NAME (sparc64,std_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_IMM_CODE + +do { + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = GET_H_GR (((f_rd) + (1))); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDHI (f_simm13, 4)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* std-reg+reg/asi: std $rdd,[$rs1+$rs2]$asi */ + +SEM_STATUS +SEM_FN_NAME (sparc64,std_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_ASI_CODE + +do { + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = GET_H_GR (((f_rd) + (1))); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* fp-ld-reg+reg: ld [$rs1+$rs2],$frd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,fp_ld_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_FP_LD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_REG_CODE + +do { +sparc64_hw_trap (current_cpu, pc, TRAP32_FP_DIS); + { + SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + CPU (h_fr[f_rd]) = opval; + TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* fp-ld-reg+imm: ld [$rs1+$simm13],$frd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,fp_ld_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_FP_LD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_IMM_CODE + +do { +sparc64_hw_trap (current_cpu, pc, TRAP32_FP_DIS); + { + SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + CPU (h_fr[f_rd]) = opval; + TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* fp-ld-reg+reg/asi: ld [$rs1+$rs2]$asi,$frd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,fp_ld_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE + +do { +sparc64_hw_trap (current_cpu, pc, TRAP32_FP_DIS); + { + SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + CPU (h_fr[f_rd]) = opval; + TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sethi: sethi $hi22,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,sethi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_SETHI_VARS /* f-hi22 f-op2 f-rd f-op */ + EXTRACT_IFMT_SETHI_CODE + + { + SI opval = SLLSI (f_hi22, 10); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* add: add $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* add-imm: add $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,add_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sub: sub $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = SUBSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sub-imm: sub $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,sub_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = SUBSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addcc: addcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,addcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { +do { + SI tmp_x; + tmp_x = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + { + BI opval = ADDCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = ADDOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addcc-imm: addcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,addcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { +do { + SI tmp_x; + tmp_x = ADDCSI (GET_H_GR (f_rs1), f_simm13, 0); + { + BI opval = ADDCFSI (GET_H_GR (f_rs1), f_simm13, 0); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = ADDOFSI (GET_H_GR (f_rs1), f_simm13, 0); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subcc: subcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,subcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { +do { + SI tmp_x; + tmp_x = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + { + BI opval = SUBCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = SUBOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = SUBSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subcc-imm: subcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,subcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { +do { + SI tmp_x; + tmp_x = SUBCSI (GET_H_GR (f_rs1), f_simm13, 0); + { + BI opval = SUBCFSI (GET_H_GR (f_rs1), f_simm13, 0); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = SUBOFSI (GET_H_GR (f_rs1), f_simm13, 0); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = SUBSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addc: addc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addc-imm: addc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,addc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subc: subc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,subc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subc-imm: subc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,subc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addccc: addccc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,addccc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { +do { + SI tmp_x; + tmp_x = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + { + BI opval = ADDCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = ADDOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addccc-imm: addccc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,addccc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { +do { + SI tmp_x; + tmp_x = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + { + BI opval = ADDCFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = ADDOFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subccc: subccc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,subccc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { +do { + SI tmp_x; + tmp_x = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + { + BI opval = SUBCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = SUBOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subccc-imm: subccc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,subccc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { +do { + SI tmp_x; + tmp_x = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + { + BI opval = SUBCFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = SUBOFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* and: and $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* and-imm: and $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,and_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = ANDSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andcc: andcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,andcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andcc-imm: andcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,andcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ANDSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* or: or $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* or-imm: or $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,or_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = ORSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orcc: orcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,orcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orcc-imm: orcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,orcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (ORSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ORSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ORSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xor: xor $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xor-imm: xor $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,xor_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xorcc: xorcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,xorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xorcc-imm: xorcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,xorcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (XORSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (XORSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andn: andn $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,andn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andn-imm: andn $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,andn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andncc: andncc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,andncc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andncc-imm: andncc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,andncc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orn: orn $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,orn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orn-imm: orn $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,orn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orncc: orncc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,orncc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orncc-imm: orncc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,orncc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xnor: xnor $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,xnor) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xnor-imm: xnor $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,xnor_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xnorcc: xnorcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,xnorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xnorcc-imm: xnorcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,xnorcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sll: sll $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = SLLSI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sll-imm: sll $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,sll_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = SLLSI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* srl: srl $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = SRLSI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* srl-imm: srl $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,srl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = SRLSI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sra: sra $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = SRASI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sra-imm: sra $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,sra_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = SRASI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* smul: smul $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,smul) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { + DI tmp_res; + tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTSIDI (GET_H_GR (f_rs2))); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* smul-imm: smul $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,smul_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { + DI tmp_res; + tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTHIDI (f_simm13)); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* smul-cc: smulcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,smul_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { + DI tmp_res; + tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTSIDI (GET_H_GR (f_rs2))); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* smul-cc-imm: smulcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,smul_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { + DI tmp_res; + tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTHIDI (f_simm13)); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* umul: umul $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,umul) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { + DI tmp_res; + tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTSIDI (GET_H_GR (f_rs2))); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* umul-imm: umul $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,umul_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { + DI tmp_res; + tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTHIDI (f_simm13)); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* umul-cc: umulcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,umul_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { + DI tmp_res; + tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTSIDI (GET_H_GR (f_rs2))); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* umul-cc-imm: umulcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,umul_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { + DI tmp_res; + tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTHIDI (f_simm13)); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* mulscc: mulscc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,mulscc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { + SI tmp_rd_tmp; + SI tmp_add_tmp; + SI tmp_tmp; + tmp_tmp = SRLSI (GET_H_GR (f_rs1), 1); +if (NEBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)), 0)) { + tmp_tmp = ORSI (tmp_tmp, 0x80000000); +} +if (NESI (ANDSI (GET_H_Y (), 1), 0)) { + tmp_add_tmp = GET_H_GR (f_rs2); +} else { + tmp_add_tmp = 0; +} + tmp_rd_tmp = ADDSI (tmp_tmp, tmp_add_tmp); +do { + SI tmp_x; + tmp_x = ADDCSI (tmp_tmp, tmp_add_tmp, 0); + { + BI opval = ADDCFSI (tmp_tmp, tmp_add_tmp, 0); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = ADDOFSI (tmp_tmp, tmp_add_tmp, 0); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = SRLSI (GET_H_Y (), 1); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } +if (NESI (ANDSI (GET_H_GR (f_rs1), 1), 0)) { + { + SI opval = ORSI (GET_H_Y (), 0x80000000); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } +} + { + SI opval = tmp_rd_tmp; + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* save: save $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,save) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = sparc64_do_save (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* save-imm: save $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,save_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = sparc64_do_save (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* restore: restore $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,restore) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + + { + SI opval = sparc64_do_restore (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* restore-imm: restore $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,restore_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + + { + SI opval = sparc64_do_restore (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* rett: rett $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,rett) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_FLUSH_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FLUSH_CODE + +do { + { + USI opval = sparc64_do_rett (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* rett-imm: rett $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,rett_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_FLUSH_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FLUSH_IMM_CODE + +do { + { + USI opval = sparc64_do_rett (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* unimp: unimp $imm22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,unimp) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_UNIMP_VARS /* f-imm22 f-op2 f-rd-res f-op */ + EXTRACT_IFMT_UNIMP_CODE + +sparc_do_unimp (current_cpu, pc, f_imm22); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* call: call $disp30 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_CALL_VARS /* f-disp30 f-op */ + IADDR i_disp30; + EXTRACT_IFMT_CALL_CODE + i_disp30 = f_disp30; + +do { + { + SI opval = pc; + SET_H_GR (((UINT) 15), opval); + TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); + } +do { + { + USI opval = i_disp30; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} while (0); +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* jmpl: jmpl $rs1+$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,jmpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +do { + { + SI opval = pc; + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + USI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} while (0); +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* jmpl-imm: jmpl $rs1+$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,jmpl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +do { + { + SI opval = pc; + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + USI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} while (0); +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* ba: ba$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ba) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +do { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} while (0); +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* ta: ta $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ta) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* ta-imm: ta $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ta_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bn: bn$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_BA_CODE + +do { +do { +do { } while (0); /*nop*/ +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tn: tn $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +do { } while (0); /*nop*/ + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tn-imm: tn $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +do { } while (0); /*nop*/ + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bne: bne$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_icc_z))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tne: tne $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (CPU (h_icc_z))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tne-imm: tne $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tne_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (CPU (h_icc_z))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* be: be$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,be) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_icc_z)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* te: te $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,te) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (CPU (h_icc_z)) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* te-imm: te $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,te_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (CPU (h_icc_z)) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bg: bg$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tg: tg $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tg-imm: tg $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* ble: ble$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tle: tle $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tle) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tle-imm: tle $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tle_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bge: bge$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tge: tge $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tge) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tge-imm: tge $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tge_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bl: bl$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tl: tl $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tl-imm: tl $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bgu: bgu$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tgu: tgu $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tgu-imm: tgu $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tgu_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bleu: bleu$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tleu: tleu $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tleu-imm: tleu $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tleu_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bcc: bcc$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_icc_c))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tcc: tcc $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (CPU (h_icc_c))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tcc-imm: tcc $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (CPU (h_icc_c))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bcs: bcs$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_icc_c)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tcs: tcs $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (CPU (h_icc_c)) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tcs-imm: tcs $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tcs_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (CPU (h_icc_c)) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpos: bpos$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bpos) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_icc_n))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tpos: tpos $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tpos) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (CPU (h_icc_n))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tpos-imm: tpos $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tpos_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (CPU (h_icc_n))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bneg: bneg$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bneg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_icc_n)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tneg: tneg $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tneg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (CPU (h_icc_n)) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tneg-imm: tneg $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tneg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (CPU (h_icc_n)) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bvc: bvc$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bvc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_icc_v))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tvc: tvc $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tvc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (CPU (h_icc_v))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tvc-imm: tvc $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tvc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (CPU (h_icc_v))) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bvs: bvs$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,bvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_icc_v)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tvs: tvs $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (CPU (h_icc_v)) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tvs-imm: tvs $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc64,tvs_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (CPU (h_icc_v)) { + { + USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* ldstub-reg+reg: ldstub [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldstub_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +sparc64_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), -1); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldstub-reg+imm: ldstub [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldstub_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +sparc64_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), f_simm13, -1); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldstub-reg+reg/asi: ldstub [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,ldstub_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + +sparc64_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), f_asi); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* swap-reg+reg: swap [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,swap_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_CODE + +sparc64_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), -1); + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* swap-reg+imm: swap [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,swap_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_IMM_CODE + +sparc64_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), f_simm13, -1); + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* swap-reg+reg/asi: swap [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc64,swap_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE + +sparc64_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), f_asi); + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + diff --git a/sim/sparc/sparc-opc.h b/sim/sparc/sparc-opc.h new file mode 100644 index 0000000000..37ec9ba782 --- /dev/null +++ b/sim/sparc/sparc-opc.h @@ -0,0 +1,175 @@ +/* Instruction opcode header for sparc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#ifndef SPARC_OPC_H +#define SPARC_OPC_H + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 256 +#undef CGEN_DIS_HASH +extern const unsigned int sparc_cgen_opcode_bits[]; +#define CGEN_DIS_HASH(buffer, insn) \ +((((insn) >> 24) & 0xc0) \ + | (((insn) & sparc_cgen_opcode_bits[((insn) >> 30) & 3]) >> 19)) + +/* -- */ +/* Enum declaration for sparc instruction types. */ +typedef enum cgen_insn_type { + SPARC_INSN_INVALID, SPARC_INSN_RD_ASR, SPARC_INSN_WR_ASR, SPARC_INSN_WR_ASR_IMM + , SPARC_INSN_RD_PSR, SPARC_INSN_WR_PSR, SPARC_INSN_WR_PSR_IMM, SPARC_INSN_RD_WIM + , SPARC_INSN_WR_WIM, SPARC_INSN_WR_WIM_IMM, SPARC_INSN_RD_TBR, SPARC_INSN_WR_TBR + , SPARC_INSN_WR_TBR_IMM, SPARC_INSN_BEQZ, SPARC_INSN_BGEZ, SPARC_INSN_BGTZ + , SPARC_INSN_BLEZ, SPARC_INSN_BLTZ, SPARC_INSN_BNEZ, SPARC_INSN_BPCC_BA + , SPARC_INSN_BPCC_BN, SPARC_INSN_BPCC_BNE, SPARC_INSN_BPCC_BE, SPARC_INSN_BPCC_BG + , SPARC_INSN_BPCC_BLE, SPARC_INSN_BPCC_BGE, SPARC_INSN_BPCC_BL, SPARC_INSN_BPCC_BGU + , SPARC_INSN_BPCC_BLEU, SPARC_INSN_BPCC_BCC, SPARC_INSN_BPCC_BCS, SPARC_INSN_BPCC_BPOS + , SPARC_INSN_BPCC_BNEG, SPARC_INSN_BPCC_BVC, SPARC_INSN_BPCC_BVS, SPARC_INSN_DONE + , SPARC_INSN_RETRY, SPARC_INSN_FLUSH, SPARC_INSN_FLUSH_IMM, SPARC_INSN_FLUSHW + , SPARC_INSN_IMPDEP1, SPARC_INSN_IMPDEP2, SPARC_INSN_MEMBAR, SPARC_INSN_MOVA_ICC_ICC + , SPARC_INSN_MOVA_IMM_ICC_ICC, SPARC_INSN_MOVA_XCC_XCC, SPARC_INSN_MOVA_IMM_XCC_XCC, SPARC_INSN_MOVN_ICC_ICC + , SPARC_INSN_MOVN_IMM_ICC_ICC, SPARC_INSN_MOVN_XCC_XCC, SPARC_INSN_MOVN_IMM_XCC_XCC, SPARC_INSN_MOVNE_ICC_ICC + , SPARC_INSN_MOVNE_IMM_ICC_ICC, SPARC_INSN_MOVNE_XCC_XCC, SPARC_INSN_MOVNE_IMM_XCC_XCC, SPARC_INSN_MOVE_ICC_ICC + , SPARC_INSN_MOVE_IMM_ICC_ICC, SPARC_INSN_MOVE_XCC_XCC, SPARC_INSN_MOVE_IMM_XCC_XCC, SPARC_INSN_MOVG_ICC_ICC + , SPARC_INSN_MOVG_IMM_ICC_ICC, SPARC_INSN_MOVG_XCC_XCC, SPARC_INSN_MOVG_IMM_XCC_XCC, SPARC_INSN_MOVLE_ICC_ICC + , SPARC_INSN_MOVLE_IMM_ICC_ICC, SPARC_INSN_MOVLE_XCC_XCC, SPARC_INSN_MOVLE_IMM_XCC_XCC, SPARC_INSN_MOVGE_ICC_ICC + , SPARC_INSN_MOVGE_IMM_ICC_ICC, SPARC_INSN_MOVGE_XCC_XCC, SPARC_INSN_MOVGE_IMM_XCC_XCC, SPARC_INSN_MOVL_ICC_ICC + , SPARC_INSN_MOVL_IMM_ICC_ICC, SPARC_INSN_MOVL_XCC_XCC, SPARC_INSN_MOVL_IMM_XCC_XCC, SPARC_INSN_MOVGU_ICC_ICC + , SPARC_INSN_MOVGU_IMM_ICC_ICC, SPARC_INSN_MOVGU_XCC_XCC, SPARC_INSN_MOVGU_IMM_XCC_XCC, SPARC_INSN_MOVLEU_ICC_ICC + , SPARC_INSN_MOVLEU_IMM_ICC_ICC, SPARC_INSN_MOVLEU_XCC_XCC, SPARC_INSN_MOVLEU_IMM_XCC_XCC, SPARC_INSN_MOVCC_ICC_ICC + , SPARC_INSN_MOVCC_IMM_ICC_ICC, SPARC_INSN_MOVCC_XCC_XCC, SPARC_INSN_MOVCC_IMM_XCC_XCC, SPARC_INSN_MOVCS_ICC_ICC + , SPARC_INSN_MOVCS_IMM_ICC_ICC, SPARC_INSN_MOVCS_XCC_XCC, SPARC_INSN_MOVCS_IMM_XCC_XCC, SPARC_INSN_MOVPOS_ICC_ICC + , SPARC_INSN_MOVPOS_IMM_ICC_ICC, SPARC_INSN_MOVPOS_XCC_XCC, SPARC_INSN_MOVPOS_IMM_XCC_XCC, SPARC_INSN_MOVNEG_ICC_ICC + , SPARC_INSN_MOVNEG_IMM_ICC_ICC, SPARC_INSN_MOVNEG_XCC_XCC, SPARC_INSN_MOVNEG_IMM_XCC_XCC, SPARC_INSN_MOVVC_ICC_ICC + , SPARC_INSN_MOVVC_IMM_ICC_ICC, SPARC_INSN_MOVVC_XCC_XCC, SPARC_INSN_MOVVC_IMM_XCC_XCC, SPARC_INSN_MOVVS_ICC_ICC + , SPARC_INSN_MOVVS_IMM_ICC_ICC, SPARC_INSN_MOVVS_XCC_XCC, SPARC_INSN_MOVVS_IMM_XCC_XCC, SPARC_INSN_LDSB_REG_REG + , SPARC_INSN_LDSB_REG_IMM, SPARC_INSN_LDSB_REG_REG_ASI, SPARC_INSN_LDUB_REG_REG, SPARC_INSN_LDUB_REG_IMM + , SPARC_INSN_LDUB_REG_REG_ASI, SPARC_INSN_LDSH_REG_REG, SPARC_INSN_LDSH_REG_IMM, SPARC_INSN_LDSH_REG_REG_ASI + , SPARC_INSN_LDUH_REG_REG, SPARC_INSN_LDUH_REG_IMM, SPARC_INSN_LDUH_REG_REG_ASI, SPARC_INSN_LDSW_REG_REG + , SPARC_INSN_LDSW_REG_IMM, SPARC_INSN_LDSW_REG_REG_ASI, SPARC_INSN_LDUW_REG_REG, SPARC_INSN_LDUW_REG_IMM + , SPARC_INSN_LDUW_REG_REG_ASI, SPARC_INSN_LDX_REG_REG, SPARC_INSN_LDX_REG_IMM, SPARC_INSN_LDX_REG_REG_ASI + , SPARC_INSN_LD_REG_REG, SPARC_INSN_LD_REG_IMM, SPARC_INSN_LD_REG_REG_ASI, SPARC_INSN_LDD_REG_REG + , SPARC_INSN_LDD_REG_IMM, SPARC_INSN_LDD_REG_REG_ASI, SPARC_INSN_STB_REG_REG, SPARC_INSN_STB_REG_IMM + , SPARC_INSN_STB_REG_REG_ASI, SPARC_INSN_STH_REG_REG, SPARC_INSN_STH_REG_IMM, SPARC_INSN_STH_REG_REG_ASI + , SPARC_INSN_ST_REG_REG, SPARC_INSN_ST_REG_IMM, SPARC_INSN_ST_REG_REG_ASI, SPARC_INSN_STX_REG_REG + , SPARC_INSN_STX_REG_IMM, SPARC_INSN_STX_REG_REG_ASI, SPARC_INSN_STD_REG_REG, SPARC_INSN_STD_REG_IMM + , SPARC_INSN_STD_REG_REG_ASI, SPARC_INSN_FP_LD_REG_REG, SPARC_INSN_FP_LD_REG_IMM, SPARC_INSN_FP_LD_REG_REG_ASI + , SPARC_INSN_SETHI, SPARC_INSN_ADD, SPARC_INSN_ADD_IMM, SPARC_INSN_SUB + , SPARC_INSN_SUB_IMM, SPARC_INSN_ADDCC, SPARC_INSN_ADDCC_IMM, SPARC_INSN_SUBCC + , SPARC_INSN_SUBCC_IMM, SPARC_INSN_ADDX, SPARC_INSN_ADDX_IMM, SPARC_INSN_SUBX + , SPARC_INSN_SUBX_IMM, SPARC_INSN_ADDXCC, SPARC_INSN_ADDXCC_IMM, SPARC_INSN_SUBXCC + , SPARC_INSN_SUBXCC_IMM, SPARC_INSN_ADDC, SPARC_INSN_ADDC_IMM, SPARC_INSN_SUBC + , SPARC_INSN_SUBC_IMM, SPARC_INSN_ADDCCC, SPARC_INSN_ADDCCC_IMM, SPARC_INSN_SUBCCC + , SPARC_INSN_SUBCCC_IMM, SPARC_INSN_AND, SPARC_INSN_AND_IMM, SPARC_INSN_ANDCC + , SPARC_INSN_ANDCC_IMM, SPARC_INSN_OR, SPARC_INSN_OR_IMM, SPARC_INSN_ORCC + , SPARC_INSN_ORCC_IMM, SPARC_INSN_XOR, SPARC_INSN_XOR_IMM, SPARC_INSN_XORCC + , SPARC_INSN_XORCC_IMM, SPARC_INSN_ANDN, SPARC_INSN_ANDN_IMM, SPARC_INSN_ANDNCC + , SPARC_INSN_ANDNCC_IMM, SPARC_INSN_ORN, SPARC_INSN_ORN_IMM, SPARC_INSN_ORNCC + , SPARC_INSN_ORNCC_IMM, SPARC_INSN_XNOR, SPARC_INSN_XNOR_IMM, SPARC_INSN_XNORCC + , SPARC_INSN_XNORCC_IMM, SPARC_INSN_SLL, SPARC_INSN_SLL_IMM, SPARC_INSN_SRL + , SPARC_INSN_SRL_IMM, SPARC_INSN_SRA, SPARC_INSN_SRA_IMM, SPARC_INSN_SMUL + , SPARC_INSN_SMUL_IMM, SPARC_INSN_SMUL_CC, SPARC_INSN_SMUL_CC_IMM, SPARC_INSN_UMUL + , SPARC_INSN_UMUL_IMM, SPARC_INSN_UMUL_CC, SPARC_INSN_UMUL_CC_IMM, SPARC_INSN_SDIV + , SPARC_INSN_SDIV_IMM, SPARC_INSN_SDIV_CC, SPARC_INSN_SDIV_CC_IMM, SPARC_INSN_UDIV + , SPARC_INSN_UDIV_IMM, SPARC_INSN_UDIV_CC, SPARC_INSN_UDIV_CC_IMM, SPARC_INSN_MULSCC + , SPARC_INSN_SAVE, SPARC_INSN_SAVE_IMM, SPARC_INSN_RESTORE, SPARC_INSN_RESTORE_IMM + , SPARC_INSN_RETT, SPARC_INSN_RETT_IMM, SPARC_INSN_UNIMP, SPARC_INSN_CALL + , SPARC_INSN_JMPL, SPARC_INSN_JMPL_IMM, SPARC_INSN_BA, SPARC_INSN_TA + , SPARC_INSN_TA_IMM, SPARC_INSN_BN, SPARC_INSN_TN, SPARC_INSN_TN_IMM + , SPARC_INSN_BNE, SPARC_INSN_TNE, SPARC_INSN_TNE_IMM, SPARC_INSN_BE + , SPARC_INSN_TE, SPARC_INSN_TE_IMM, SPARC_INSN_BG, SPARC_INSN_TG + , SPARC_INSN_TG_IMM, SPARC_INSN_BLE, SPARC_INSN_TLE, SPARC_INSN_TLE_IMM + , SPARC_INSN_BGE, SPARC_INSN_TGE, SPARC_INSN_TGE_IMM, SPARC_INSN_BL + , SPARC_INSN_TL, SPARC_INSN_TL_IMM, SPARC_INSN_BGU, SPARC_INSN_TGU + , SPARC_INSN_TGU_IMM, SPARC_INSN_BLEU, SPARC_INSN_TLEU, SPARC_INSN_TLEU_IMM + , SPARC_INSN_BCC, SPARC_INSN_TCC, SPARC_INSN_TCC_IMM, SPARC_INSN_BCS + , SPARC_INSN_TCS, SPARC_INSN_TCS_IMM, SPARC_INSN_BPOS, SPARC_INSN_TPOS + , SPARC_INSN_TPOS_IMM, SPARC_INSN_BNEG, SPARC_INSN_TNEG, SPARC_INSN_TNEG_IMM + , SPARC_INSN_BVC, SPARC_INSN_TVC, SPARC_INSN_TVC_IMM, SPARC_INSN_BVS + , SPARC_INSN_TVS, SPARC_INSN_TVS_IMM, SPARC_INSN_LDSTUB_REG_REG, SPARC_INSN_LDSTUB_REG_IMM + , SPARC_INSN_LDSTUB_REG_REG_ASI, SPARC_INSN_SWAP_REG_REG, SPARC_INSN_SWAP_REG_IMM, SPARC_INSN_SWAP_REG_REG_ASI + , SPARC_INSN_MAX +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID SPARC_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) SPARC_INSN_MAX) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_op; + long f_op2; + long f_op3; + long f_rs1; + long f_rs2; + long f_rd; + long f_rd_res; + long f_i; + long f_simm13; + long f_imm22; + long f_hi22; + long f_a; + long f_fmt2_cond; + long f_disp22; + long f_disp30; + long f_opf; + long f_res_12_8; + long f_simm10; + long f_fmt2_cc; + long f_fmt3_cc; + long f_x; + long f_shcnt32; + long f_fcn; + long f_imm_asi; + long f_asi; + long f_res_asi; + long f_fmt4_cc; + long f_soft_trap; + long f_opf_low5; + long f_opf_low6; + long f_opf_cc; + long f_fmt2_cc1; + long f_fmt2_cc0; + long f_p; + long f_fmt2_rcond; + long f_disp19; + long f_fmt3_rcond; + long f_shcnt64; + long f_fmt4_cond; + long f_fmt4_ccx_hi; + long f_fmt4_ccx_lo; + long f_fmt4_rcond; + long f_fmt4_cc2; + long f_fmt4_cc1_0; + long f_fmt4_res10_6; + long f_disp16_hi; + long f_disp16_lo; + long f_disp16; + long f_res_18_19; + long f_bpr_res28_1; + long f_impdep5; + long f_impdep19; + long f_membar_res12_6; + long f_cmask; + long f_mmask; + long f_membarmask; + long f_simm11; +}; + + + +#endif /* SPARC_OPC_H */ diff --git a/sim/sparc/trap64.c b/sim/sparc/trap64.c new file mode 100644 index 0000000000..f87160f415 --- /dev/null +++ b/sim/sparc/trap64.c @@ -0,0 +1,308 @@ +/* sparc64 trap support + Copyright (C) 1999 Cygnus Solutions. */ + +#define WANT_CPU sparc64 +#define WANT_CPU_SPARC64 + +#include "sim-main.h" +#include "targ-vals.h" + +/* Indicate a window overflow has occured. */ + +void +sparc64_window_overflow (SIM_CPU *cpu, IADDR pc) +{ + SIM_DESC sd = CPU_STATE (cpu); + + if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) + sparc64_hw_trap (cpu, pc, TRAP32_WINDOW_OVERFLOW); + else + sparc64_hw_trap (cpu, pc, TRAP32_SIM_SPILL); +} + +/* Indicate a window underflow has occured. */ + +void +sparc64_window_underflow (SIM_CPU *cpu, IADDR pc) +{ + SIM_DESC sd = CPU_STATE (cpu); + + if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) + sparc64_hw_trap (cpu, pc, TRAP32_WINDOW_UNDERFLOW); + else + sparc64_hw_trap (cpu, pc, TRAP32_SIM_FILL); +} + +void +sparc64_invalid_insn (SIM_CPU * cpu, IADDR pc) +{ + sparc64_hw_trap (cpu, pc, TRAP32_ILLEGAL_INSN); +} + +void +sparc64_core_signal (SIM_DESC sd, SIM_CPU *cpu, sim_cia pc, + unsigned int map, int nr_bytes, address_word addr, + transfer_type transfer, sim_core_signals sig) +{ + sparc64_hw_trap (cpu, pc, + map == exec_map + ? TRAP32_INSTRUCTION_ACCESS + : TRAP32_DATA_ACCESS); +} + +/* Handle hardware generated traps when --environment=operating. */ + +static void +sparc64_hw_trap_oper (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + IADDR new_pc = (GET_H_TBR () & 0xfffff000) | (trap << 4); + USI psr = GET_H_PSR (); + + psr &= ~PSR_ET; + psr = (psr & ~PSR_PS) | (psr & PSR_S ? PSR_PS : 0); + psr |= PSR_S; + psr = (psr & ~PSR_CWP) | NEXT_WIN (psr & PSR_CWP); + SET_H_PSR (psr); + SET_H_GR (H_GR__L1, GET_H_PC ()); + SET_H_GR (H_GR__L2, GET_H_NPC ()); + + SET_H_ANNUL_P (0); + + /* The wrtbr insn doesn't affect the tt part so SET_H_TBR doesn't either + (??? doesn't *have* to be this way though). + Therefore we can't use SET_H_TBR here. */ + CPU (h_tbr) = new_pc; + SET_H_PC (new_pc); + SET_H_NPC (new_pc + 4); + + sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, new_pc); +} + +/* Handle hardware generated traps when --environment=user. */ + +static void +sparc64_hw_trap_user (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + + switch (trap) + { + case TRAP32_SIM_SPILL : + /* The CWP-1 window is invalid. */ + { + int win = NEXT_WIN (GET_H_CWP ()); + int next_win = NEXT_WIN (win); + int nwindows = GET_NWINDOWS (); + unsigned int mask = (1 << nwindows) - 1; + unsigned int wim = GET_H_WIM (); + + /* There's no need to flush `current_regs' here, `next_win' can't + refer to it. */ + sparc64_flush_regwin (current_cpu, pc, next_win, 0 /* error ok (?) */); + /* Rotate WIM right one. */ + wim = ((wim & mask) >> 1) | (wim << (nwindows - 1)); + SET_H_WIM (wim & mask); + return; + } + + case TRAP32_SIM_FILL : + /* The CWP+1 window is invalid. */ + { + int win = PREV_WIN (GET_H_CWP ()); + int nwindows = GET_NWINDOWS (); + unsigned int mask = (1 << nwindows) - 1; + unsigned int wim = GET_H_WIM (); + + /* Load caller's caller's window. + There's no need to flush `current_regs' as `win' can't + refer to it. */ + sparc64_load_regwin (current_cpu, pc, win); + /* Rotate WIM left one. */ + wim = (wim << 1) | ((wim & mask) >> (nwindows - 1)); + SET_H_WIM (wim & mask); + return; + } + } + + sim_io_eprintf (sd, "Received trap %d\n", trap); + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGABRT); +} + +/* Handle hardware generated traps. */ + +void +sparc64_hw_trap (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + + if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) + sparc64_hw_trap_oper (current_cpu, pc, trap); + else + sparc64_hw_trap_user (current_cpu, pc, trap); +} + +/* Handle the trap insn when --environment=operating. */ + +static IADDR +sparc64_sw_trap_oper (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + int trap = 128 + ((rs1 + rs2_simm13) & 127); + IADDR new_pc; + + /* ??? Quick hack to have breakpoints work with gdb+"target sim" until + other things are working. */ + if (trap == TRAP32_BREAKPOINT) + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); + + if (! GET_H_ET ()) + { + /* Enter error mode. + ??? wip, need to remain compatible with erc32 for now. */ + int i0 = GET_H_GR (H_GR__I0); + int i1 = GET_H_GR (H_GR__I1); + + if (i1 == LIBGLOSS_EXIT_MAGIC) + sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, i0); + else + { + sim_io_eprintf (sd, "Unexpected program termination, pc=0x%x\n", + (int) pc); + sim_engine_halt (sd, current_cpu, NULL, pc, + sim_signalled, SIM_SIGABRT); + } + } + + SET_H_ET (0); + SET_H_PSR ((GET_H_PSR () & ~(PSR_CWP | PSR_PS)) + | PSR_S + | (GET_H_S () ? PSR_PS : 0) + | (NEXT_WIN (GET_H_CWP ()))); + SET_H_GR (H_GR__L1, GET_H_PC ()); + SET_H_GR (H_GR__L2, GET_H_NPC ()); + /* The wrtbr insn doesn't affect the tt part so SET_H_TBR doesn't either + (??? doesn't *have* to be this way though). + Therefore we can't use SET_H_TBR here. */ + CPU (h_tbr) = new_pc = ((GET_H_TBR () & 0xfffff000) + | (trap << 4)); + return new_pc; +} + +/* Subroutine of sparc64_do_trap to read target memory. */ + +static int +syscall_read_mem (host_callback *cb, CB_SYSCALL *sc, + unsigned long taddr, char *buf, int bytes) +{ + SIM_DESC sd = (SIM_DESC) sc->p1; + SIM_CPU *cpu = (SIM_CPU *) sc->p2; + + return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); +} + +/* Subroutine of sparc64_do_trap to write target memory. */ + +static int +syscall_write_mem (host_callback *cb, CB_SYSCALL *sc, + unsigned long taddr, const char *buf, int bytes) +{ + SIM_DESC sd = (SIM_DESC) sc->p1; + SIM_CPU *cpu = (SIM_CPU *) sc->p2; + + return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); +} + +/* Handle the trap insn when --environment=user. */ + +static IADDR +sparc64_sw_trap_user (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + int trap = 128 + ((rs1 + rs2_simm13) & 127); + IADDR new_pc = pc + 4; + + switch (trap) + { + case TRAP32_SYSCALL : + /* FIXME: Later make trap number runtime selectable. */ + { + CB_SYSCALL s; + + CB_SYSCALL_INIT (&s); + s.func = a_sparc_h_gr_get (current_cpu, 8); + s.arg1 = a_sparc_h_gr_get (current_cpu, 9); + s.arg2 = a_sparc_h_gr_get (current_cpu, 10); + s.arg3 = a_sparc_h_gr_get (current_cpu, 11); + if (s.func == TARGET_SYS_exit) + { + /* Tell sim_resume program called exit(). */ + sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1); + } + s.p1 = (PTR) sd; + s.p2 = (PTR) current_cpu; + s.read_mem = syscall_read_mem; + s.write_mem = syscall_write_mem; + cb_syscall (STATE_CALLBACK (CPU_STATE (current_cpu)), &s); + a_sparc_h_gr_set (current_cpu, 10, s.errcode); + a_sparc_h_gr_set (current_cpu, 8, s.result); + a_sparc_h_gr_set (current_cpu, 9, s.result2); + break; + } + + case TRAP32_BREAKPOINT : + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); + + case TRAP32_DIVIDE_0 : + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE); + + case TRAP32_FLUSH_REGWIN : + sparc64_flush_regwins (current_cpu, pc, 0 /* error ok */); + break; + + default : + sim_io_eprintf (sd, "Unsupported trap %d\n", trap); + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGILL); + } + + return new_pc; +} + +/* Called from the semantic code to handle the trap instruction. */ + +IADDR +sparc64_sw_trap (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + IADDR new_pc; + + if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) + new_pc = sparc64_sw_trap_oper (current_cpu, pc, rs1, rs2_simm13); + else + new_pc = sparc64_sw_trap_user (current_cpu, pc, rs1, rs2_simm13); + return new_pc; +} + +/* Handle the rett insn. */ + +IADDR +sparc64_do_rett (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) +{ + int psr = GET_H_PSR (); + + /* FIXME: check for trap conditions. */ + + SET_H_PSR ((psr & ~(PSR_S + PSR_CWP)) + | ((psr & PSR_PS) ? PSR_S : 0) + | PSR_ET + | PREV_WIN (psr & PSR_CWP)); + + if (TRACE_INSN_P (current_cpu)) /* FIXME */ + { + trace_result (current_cpu, "sp", 'x', GET_H_GR (H_GR__SP)); + trace_result (current_cpu, "fp", 'x', GET_H_GR (H_GR__FP)); + trace_result (current_cpu, "cwp", 'x', GET_H_CWP ()); + } + + return rs1 + rs2_simm13; +}