From: Lucas Stach Date: Mon, 29 Feb 2016 20:46:06 +0000 (+0100) Subject: clk: tegra: Initialize PLL_C to sane rate on Tegra30 X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=a02cc84a31d3bd46a10546ff7024e7b5a186d339;p=deliverable%2Flinux.git clk: tegra: Initialize PLL_C to sane rate on Tegra30 If the bootloader does not touch PLL_C it will stay in its reset state, failing to lock when enabled. This leads to consumers of this clock to fail probing. Fix this by always programming the PLL with a sane rate, which allows it to lock, at startup. Signed-off-by: Lucas Stach Signed-off-by: Thierry Reding --- diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 0478565cf292..236e2db9a716 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1372,6 +1372,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 }, { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 }, { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 }, + { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 }, { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 }, { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },