From: H Hartley Sweeten Date: Fri, 1 May 2015 21:58:38 +0000 (-0700) Subject: staging: comedi: ni_stc.h: tidy up NI_M_PLL_STATUS_REG bits X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=b1c70645286c50e9fb5338b45d388e1176e881d5;p=deliverable%2Flinux.git staging: comedi: ni_stc.h: tidy up NI_M_PLL_STATUS_REG bits Rename the CamelCase and convert the enum into defines. Use the BIT() macro to define the bits. Signed-off-by: H Hartley Sweeten Reviewed-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c index 0a1f92e43b5d..bb4fde0e777c 100644 --- a/drivers/staging/comedi/drivers/ni_mio_common.c +++ b/drivers/staging/comedi/drivers/ni_mio_common.c @@ -4740,7 +4740,7 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, devpriv->clock_source = source; /* it seems to typically take a few hundred microseconds for PLL to lock */ for (i = 0; i < timeout; ++i) { - if (ni_readw(dev, NI_M_PLL_STATUS_REG) & MSeries_PLL_Locked_Bit) + if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED) break; udelay(1); } diff --git a/drivers/staging/comedi/drivers/ni_stc.h b/drivers/staging/comedi/drivers/ni_stc.h index f08124e47d5b..ffed5a1c6f06 100644 --- a/drivers/staging/comedi/drivers/ni_stc.h +++ b/drivers/staging/comedi/drivers/ni_stc.h @@ -991,6 +991,7 @@ static const struct comedi_lrange range_ni_E_ao_ext; #define NI_M_PLL_MAX_MULTIPLIER 0x100 #define NI_M_PLL_CTRL_MULTIPLIER(x) (((x) & 0xff) << 0) #define NI_M_PLL_STATUS_REG 0x1c8 +#define NI_M_PLL_STATUS_LOCKED BIT(0) #define NI_M_PFI_OUT_SEL_REG(x) (0x1d0 + ((x) * 2)) #define NI_M_PFI_DI_REG 0x1dc #define NI_M_PFI_DO_REG 0x1de @@ -1007,10 +1008,6 @@ static const struct comedi_lrange range_ni_E_ao_ext; #define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064) #define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x)) -enum MSeries_PLL_Status { - MSeries_PLL_Locked_Bit = 0x1 -}; - enum MSeries_AI_Config_FIFO_Bypass_Bits { MSeries_AI_Bypass_Channel_Mask = 0x7, MSeries_AI_Bypass_Bank_Mask = 0x78,