From: Noam Camus Date: Fri, 10 Apr 2015 18:28:50 +0000 (+0300) Subject: ARC: [plat-eznps] Use dedicated SMP barriers X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=b1f2f6f3cf5e37f0418f6cebf365cff7c3abf6d7;p=deliverable%2Flinux.git ARC: [plat-eznps] Use dedicated SMP barriers NPS device got 256 cores and each got 16 HW threads (SMT). We use EZchip dedicated ISA to trigger HW scheduler of the core that current HW thread belongs to. This scheduling makes sure that data beyond barrier is available to all HW threads in core and by that to all in device (4K). Signed-off-by: Noam Camus Cc: Peter Zijlstra --- diff --git a/arch/arc/include/asm/barrier.h b/arch/arc/include/asm/barrier.h index a7209983ee64..b1e327495c7d 100644 --- a/arch/arc/include/asm/barrier.h +++ b/arch/arc/include/asm/barrier.h @@ -30,9 +30,7 @@ #define rmb() asm volatile("dmb 1\n" : : : "memory") #define wmb() asm volatile("dmb 2\n" : : : "memory") -#endif - -#ifdef CONFIG_ISA_ARCOMPACT +#elif !defined(CONFIG_ARC_PLAT_EZNPS) /* CONFIG_ISA_ARCOMPACT */ /* * ARCompact based cores (ARC700) only have SYNC instruction which is super @@ -41,6 +39,14 @@ */ #define mb() asm volatile("sync\n" : : : "memory") + +#else /* CONFIG_ARC_PLAT_EZNPS */ + +#include + +#define mb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory") +#define rmb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RD) : "memory") + #endif #include