From: Gregory Herrero <gregory.herrero@intel.com>
Date: Tue, 22 Sep 2015 13:16:49 +0000 (+0200)
Subject: usb: dwc2: host: clear pending interrupts prior hibernation
X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=cad73da26cb9392db3449ab35e506ea13efd1888;p=deliverable%2Flinux.git

usb: dwc2: host: clear pending interrupts prior hibernation

If an interrupt rises during hibernation process, dwc2 will assert
interrupt line to interrupt controller. If interrupt is level
sensitive, interrupt handler will be called in a loop because dwc2
will not be able to clear it while controller is hibernated.
Thus, clear all controller interrupts before hibernation entry.

Signed-off-by: Gregory Herrero <gregory.herrero@intel.com>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: Robert Baldyga <r.baldyga@samsung.com>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: John Youn <johnyoun@synopsys.com>
Acked-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
---

diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index c5e0a45c565d..bf5e951fbb7f 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -398,6 +398,12 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
 		}
 	}
 
+	/*
+	 * Clear any pending interrupts since dwc2 will not be able to
+	 * clear them after entering hibernation.
+	 */
+	dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
+
 	/* Put the controller in low power state */
 	pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);