From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Fri, 27 Jun 2014 23:03:59 +0000 (+0300)
Subject: drm/i915: Leave DPLL ref clocks on
X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=d17ec4ced6c0907f80f51677a44236da94ecd92d;p=deliverable%2Flinux.git

drm/i915: Leave DPLL ref clocks on

We enable the DPLL refclock already when bringing up the cmnlane power
well, so also leave it on when otherwise disabling the DPLL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a7d0c88a620d..6ca53b372a4c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1684,7 +1684,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	assert_pipe_disabled(dev_priv, pipe);
 
 	/* Set PLL en = 0 */
-	val = DPLL_SSC_REF_CLOCK_CHV;
+	val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
 	if (pipe != PIPE_A)
 		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 	I915_WRITE(DPLL(pipe), val);